aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* Archibald Rust and Clifford Wolf: ffi-based dpi_call()Clifford Wolf2014-08-223-9/+93
|
* Added "plugin" commandClifford Wolf2014-08-226-10/+136
|
* Updated ABC to 4d547a5e065bClifford Wolf2014-08-221-1/+1
|
* Cosmetic changes to FSM testsClifford Wolf2014-08-211-1/+1
|
* Fixed small memory leak in ast simplifyClifford Wolf2014-08-211-3/+3
|
* Added support for DPI function with different names in C and VerilogClifford Wolf2014-08-213-9/+20
|
* Added AstNode::asInt()Clifford Wolf2014-08-213-2/+24
|
* Fixed memory leak in DPI function callsClifford Wolf2014-08-211-0/+4
|
* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2014-08-212-63/+100
|\
| * Added mod->addGate() methods for new gate typesClifford Wolf2014-08-192-63/+100
| |
* | Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)Clifford Wolf2014-08-218-3/+135
| |
* | Added support for global tasks and functionsClifford Wolf2014-08-213-27/+49
|/
* Using "via_celltype" in $mul carry-save-acc implementationClifford Wolf2014-08-181-34/+72
|
* Added "via_celltype" attribute on task/funcClifford Wolf2014-08-183-18/+110
|
* Performance fix for new $__lcu techmap ruleClifford Wolf2014-08-181-7/+5
|
* Replaced recursive lcu scheme with bk adderClifford Wolf2014-08-181-61/+31
|
* Added const folding of AST_CASE to AST simplifierClifford Wolf2014-08-183-1/+41
|
* Fixed proc_{self,share}_dirname error handlingClifford Wolf2014-08-171-4/+2
|
* Makefile fixesClifford Wolf2014-08-171-1/+4
|
* Improved AST ProcessGenerator performanceClifford Wolf2014-08-171-3/+3
|
* Improved sig.remove2() performanceClifford Wolf2014-08-171-2/+11
|
* Use stackmap<> in AST ProcessGeneratorClifford Wolf2014-08-173-24/+22
|
* Added stackmap<> containerClifford Wolf2014-08-172-2/+109
|
* Renamed toposort.h to utils.hClifford Wolf2014-08-173-2/+2
|
* Added module->uniquify()Clifford Wolf2014-08-165-15/+29
|
* Fixed AOI/OAI expr handling in verilog backendClifford Wolf2014-08-161-4/+4
|
* Multiply using a carry-save accumulatorClifford Wolf2014-08-161-5/+45
|
* Added "test_cell -s <seed>"Clifford Wolf2014-08-161-5/+17
|
* AST ProcessGenerator: replaced subst_*_{from,to} with subst_*_mapClifford Wolf2014-08-161-41/+26
|
* Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ ↵Clifford Wolf2014-08-168-48/+399
| | | | $_OAI4_
* Added CellTypes::cell_evaluable()Clifford Wolf2014-08-161-31/+37
|
* Changes in techmap $__alu interfaceClifford Wolf2014-08-161-17/+17
|
* Added "opt -fast"Clifford Wolf2014-08-161-19/+45
|
* Added log_spacer()Clifford Wolf2014-08-163-2/+20
|
* Bugfix in iopadmapClifford Wolf2014-08-151-1/+3
|
* Renamed $lut ports to follow A-Y naming schemeClifford Wolf2014-08-156-39/+38
|
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-1519-47/+47
|
* Removed old doc references to $safe_pmuxClifford Wolf2014-08-152-5/+1
|
* More idstring sort_by_* helpers and fixed tpl ordering in techmapClifford Wolf2014-08-154-10/+22
|
* Added Frontend "+/" filename syntax for files from proc_share_dirClifford Wolf2014-08-151-1/+4
|
* document "techmap -map %<design-name>"Clifford Wolf2014-08-151-0/+3
|
* Fixed bug in "read_verilog -ignore_redef"Clifford Wolf2014-08-151-1/+1
|
* Added RTLIL::SigSpec::to_sigbit_map()Clifford Wolf2014-08-143-11/+20
|
* Changed the AST genWidthRTLIL subst interface to use a std::mapClifford Wolf2014-08-143-21/+31
|
* Added sig.{replace,remove,extract} variants for std::{map,set} patternClifford Wolf2014-08-142-25/+64
|
* Fixed line numbers when using here-doc macrosClifford Wolf2014-08-141-4/+9
|
* Fixed handling of task outputsClifford Wolf2014-08-141-2/+4
|
* Simplified $__arraymul techmap ruleClifford Wolf2014-08-141-7/+13
|
* Added module->portsClifford Wolf2014-08-149-10/+23
|
* Refactoring of CellType classClifford Wolf2014-08-143-155/+139
|
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-23 17:27:04 +0000