iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Added basic support for $expect cells	Clifford Wolf	2016-07-13	16	-19/+82
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*	Added examples/smtbmc	Clifford Wolf	2016-07-13	2	-0/+30
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*	Merge pull request #191 from whitequark/json-module-attributes	Clifford Wolf	2016-07-13	1	-2/+6
\|\ \| \| \| \|	write_json: also write module attributes
\| *	write_json: also write module attributes.	whitequark	2016-07-12	1	-2/+6
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* \|	Merge pull request #193 from azonenberg/master	Clifford Wolf	2016-07-13	2	-2/+9
\|\ \ \| \| \| \| \| \|	Removed splitnets in synth_greenpak4, added GP_DAC, refactored GP_BANDGAP
\| * \	Merge https://github.com/cliffordwolf/yosys	Andrew Zonenberg	2016-07-12	1	-2/+5
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* \| \|	Minor bugfix in FSM reset state detection	Clifford Wolf	2016-07-12	1	-2/+5
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\| *	Added GP_DAC cell	Andrew Zonenberg	2016-07-11	1	-0/+8
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\| *	Removed VOUT port of GP_BANDGAP	Andrew Zonenberg	2016-07-11	1	-1/+1
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\| *	Removed splitnets in prep for new gp4par parser	Andrew Zonenberg	2016-07-11	1	-1/+0
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*	Yosys-smtbmc: Support for hierarchical VCD dumping	Clifford Wolf	2016-07-11	2	-23/+59
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*	Moved smt2 yosys info parsing from smtbmc.py to smtio.py	Clifford Wolf	2016-07-11	3	-16/+56
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*	Added "prep -auto-top" and "synth -auto-top"	Clifford Wolf	2016-07-11	2	-6/+23
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*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2016-07-10	1	-0/+26
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\| *	Merge pull request #189 from whitequark/master	Clifford Wolf	2016-07-10	1	-0/+26
\| \|\ \| \| \| \| \| \|	greenpak4: add GP_COUNT{8,14}_ADV cells
\| \| *	greenpak4: add GP_COUNT{8,14}_ADV cells.	whitequark	2016-07-10	1	-0/+26
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* /	Support for hierarchical designs in smt2 back-end	Clifford Wolf	2016-07-10	2	-24/+144
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*	Further improved fsm_detect output, attempt to detect self-resetting circuits	Clifford Wolf	2016-07-09	1	-6/+68
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*	Added printing of some warning messages to fsm_detect	Clifford Wolf	2016-07-09	1	-14/+61
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*	Added warning about adding fsm_encoding attributes to wires to manual	Clifford Wolf	2016-07-08	1	-0/+4
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*	Minor fixes in ice40_ff* passes for sloppy SB_DFF instantiations	Clifford Wolf	2016-07-08	2	-13/+24
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*	Fixed mem assignment in left-hand-side concatenation	Clifford Wolf	2016-07-08	2	-0/+57
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*	Merge branch 'eddiehung-vtr'	Clifford Wolf	2016-07-08	1	-9/+17
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\| *	Restored blif "-true - .." behavior, use "-true + .." for eddiehung-vtr behavior	Clifford Wolf	2016-07-08	1	-13/+15
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\| *	In BLIF, a .names without entries already always outputs 0	Clifford Wolf	2016-07-08	1	-11/+0
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\| *	Undo eddiehung-vtr Makefile changes	Clifford Wolf	2016-07-08	1	-5/+1
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\| *	Merge branch 'yosys-0.5-vtr' of https://github.com/eddiehung/yosys into ↵	Clifford Wolf	2016-07-08	2	-3/+24
\|/\| \| \| \| \| \| \|	eddiehung-vtr
\| *	Fix for all zero mask	eddiehung	2015-05-03	2	-1/+16
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\| *	Escape '<' and '>' some more	eddiehung	2015-05-03	1	-1/+1
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\| *	For vtr, escape angle brackets as well	eddiehung	2015-04-28	1	-1/+1
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\| *	blifwriter: write out .names for true/false/undef type == '-'	eddiehung	2015-04-28	1	-0/+6
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* \|	Fixed autotest.sh handling of `timescale	Clifford Wolf	2016-07-02	1	-14/+10
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* \|	Merge branch 'assert-limit'	Clifford Wolf	2016-07-01	1	-9/+33
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\| * \|	Replaced "select -assert-limit" with -assert-max and -assert-min	Clifford Wolf	2016-07-01	1	-42/+29
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\| * \|	Added 'assert-limit' option for 'select' command	eshellko	2016-07-01	1	-5/+42
\|/ / \| \| \| \|	For resource limited designs such as FPGA it can be useful to specify limit of specific resources available on board. So user can check if he should change RTL as early as mapping done.
* \|	Improved ice40_ffinit error reporting	Clifford Wolf	2016-06-30	1	-1/+5
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* \|	Merge pull request #181 from rubund/input_logic_allowed	Clifford Wolf	2016-06-21	1	-2/+2
\|\ \ \| \| \| \| \| \|	Allow defining input ports as "input logic" in SystemVerilog
\| * \|	Allow defining input ports as "input logic" in SystemVerilog	Ruben Undheim	2016-06-20	1	-2/+2
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* \|	Bugfix in "abc -script" handling	Clifford Wolf	2016-06-19	1	-53/+50
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* \|	Merge branch 'sv_packages' of https://github.com/rubund/yosys	Clifford Wolf	2016-06-19	7	-1/+52
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\| * \|	A few modifications after pull request comments	Ruben Undheim	2016-06-18	3	-5/+4
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	- Renamed Design::packages to Design::verilog_packages - No need to include ast.h in rtlil.h
\| * \|	Added support for SystemVerilog packages with localparam definitions	Ruben Undheim	2016-06-18	7	-1/+53
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* \| \|	Added "deminout"	Clifford Wolf	2016-06-19	3	-0/+118
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* \| \|	Added "read_blif -sop"	Clifford Wolf	2016-06-18	1	-5/+10
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* \| \|	Added $sop support to BLIF back-end	Clifford Wolf	2016-06-18	1	-2/+29
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* \|	Added "dc2" to default ABC scripts	Clifford Wolf	2016-06-17	1	-5/+5
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* \|	Fixed init issue in mem2reg_test2 test case	Clifford Wolf	2016-06-17	1	-2/+6
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* \|	Added "abc -I <num> -P <num>"	Clifford Wolf	2016-06-17	1	-8/+33
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* \|	Added $sop SAT model	Clifford Wolf	2016-06-17	1	-0/+82
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* \|	Improved support for $sop cells	Clifford Wolf	2016-06-17	6	-10/+89
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