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* Bump versionYosys Bot2020-11-111-1/+1
* Merge pull request #2433 from YosysHQ/paths_as_globalsMiodrag Milanović2020-11-104-43/+63
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| * Expose abc and data paths as globalsMiodrag Milanovic2020-11-064-43/+63
* | Bump versionYosys Bot2020-11-081-1/+1
* | Merge pull request #2414 from zeldin/abc-depend-clang-fixwhitequark2020-11-071-0/+4
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| * | Prevent CXXFLAGS from leaking to abc MakefileMarcus Comstedt2020-11-071-0/+4
* | | Merge pull request #2432 from Xiretza/nexus-testsMiodrag Milanović2020-11-071-19/+3
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| * | Update nexus arch tests to new harnessXiretza2020-10-291-19/+3
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* | Bump versionYosys Bot2020-11-031-1/+1
* | Merge pull request #2426 from whitequark/cxxrtl-auto-topwhitequark2020-11-021-7/+26
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| * | cxxrtl: run `hierarchy -auto-top` if no top module is present.whitequark2020-11-021-7/+26
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* | Bump versionYosys Bot2020-11-021-1/+1
* | Merge pull request #2425 from whitequark/cxxrtl-meminit-constnesswhitequark2020-11-011-2/+4
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| * | cxxrtl: don't assert on non-constant $meminit inputs.whitequark2020-11-011-2/+4
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* | Merge pull request #2424 from whitequark/cxxrtl-multiple-driverswhitequark2020-11-011-0/+2
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| * | cxxrtl: don't assert on wires with multiple drivers.whitequark2020-11-011-0/+2
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* | Bump versionYosys Bot2020-11-011-1/+1
* | Merge pull request #2416 from QuantamHD/masterwhitequark2020-10-311-1/+6
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| * | This patch adds support for defining the ABC location at runtime instead of a...Ethan Mahintorabi2020-10-281-1/+6
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* | Bump versionYosys Bot2020-10-311-1/+1
* | Update verific versionMiodrag Milanovic2020-10-301-1/+1
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* Bump versionYosys Bot2020-10-251-1/+1
* xilinx: Fix attributes_test.ysMarcelina Kościelnicka2020-10-241-4/+2
* Bump versionYosys Bot2020-10-231-1/+1
* nexus: Add make_transp to BRAMsDavid Shah2020-10-221-0/+3
* Merge pull request #2403 from nakengelhardt/sim_timescaleN. Engelhardt2020-10-221-0/+21
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| * use strftime instead of put_time for gcc 4.8 compatibilityN. Engelhardt2020-10-211-4/+5
| * wild guessing at the problem because it builds fine on my machinesN. Engelhardt2020-10-161-0/+3
| * sim -vcd: add date, version, and option for timescaleN. Engelhardt2020-10-161-0/+17
* | memory_dff: Fix needlessly duplicating enable bits.Marcelina Kościelnicka2020-10-222-0/+32
* | Bump versionYosys Bot2020-10-221-1/+1
* | btor: Use Mem helper.Marcelina Kościelnicka2020-10-211-93/+102
* | smt2: Use Mem helper.Marcelina Kościelnicka2020-10-211-186/+244
* | verilog_backend: Use Mem helper.Marcelina Kościelnicka2020-10-211-274/+251
* | sim: Use Mem helper.Marcelina Kościelnicka2020-10-211-103/+90
* | clk2fflogic: Use Mem helper.Marcelina Kościelnicka2020-10-211-68/+45
* | opt_mem: Use Mem helpers.Marcelina Kościelnicka2020-10-211-81/+6
* | memory_bram: Use Mem helpers.Marcelina Kościelnicka2020-10-211-121/+90
* | memory_map: Use Mem helpers.Marcelina Kościelnicka2020-10-211-138/+81
* | memory_unpack: Use Mem helpers.Marcelina Kościelnicka2020-10-211-106/+10
* | memory_collect: Use Mem helpers.Marcelina Kościelnicka2020-10-211-223/+9
* | memory_nordff: Use Mem helpers.Marcelina Kościelnicka2020-10-211-63/+9
* | Add new helper structures to represent memories.Marcelina Kościelnicka2020-10-213-1/+516
* | Bump versionYosys Bot2020-10-211-1/+1
* | Merge pull request #2405 from byuccl/fix_xilinx_cellsclairexen2020-10-201-2/+2
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| * | Move signal declarations to before first useJeff Goeders2020-10-191-2/+2
* | | Merge pull request #2404 from YosysHQ/claire/fixrpcargsclairexen2020-10-201-1/+2
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| * | | Fix argument handling in connect_rpcClaire Xenia Wolf2020-10-191-1/+2
* | | | Bump versionYosys Bot2020-10-201-1/+1
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* | | Merge pull request #2397 from daveshah1/nexusMiodrag Milanović2020-10-1930-0/+12528
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