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* | | | | | | | Merge pull request #1117 from bwidawsk/more-homeClifford Wolf2019-06-212-0/+5
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| * | | | | | | | Add a few more filename rewritesBen Widawsky2019-06-202-0/+5
* | | | | | | | | Merge pull request #1119 from YosysHQ/eddie/fix1118Clifford Wolf2019-06-212-0/+12
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| * | | | | | | | | Add testEddie Hung2019-06-201-0/+11
| * | | | | | | | | Make genvar a signed typeEddie Hung2019-06-201-0/+1
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* | | | | | | | | Merge pull request #1116 from YosysHQ/eddie/fix1115Clifford Wolf2019-06-213-7/+41
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| * | | | | | | | Add CHANGELOG entryEddie Hung2019-06-201-1/+2
| * | | | | | | | Extend sign extension testsEddie Hung2019-06-201-4/+16
| * | | | | | | | Maintain "is_unsized" state of constantsEddie Hung2019-06-201-6/+6
| * | | | | | | | Revert "Fix sign extension when sign is 1'bx"Eddie Hung2019-06-201-1/+1
| * | | | | | | | Remove leftover commentEddie Hung2019-06-201-3/+0
| * | | | | | | | Add testEddie Hung2019-06-201-0/+24
| * | | | | | | | Fix sign extension when sign is 1'bxEddie Hung2019-06-201-1/+1
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* / / / / / / / Fix gcc invalidation behaviour for write_aigerEddie Hung2019-06-201-1/+2
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* | | | | | | Fix typo, fixes #1095Clifford Wolf2019-06-201-1/+1
* | | | | | | Improve shregmap help message, fixes #1113Clifford Wolf2019-06-201-0/+2
* | | | | | | Update some .gitignore filesClifford Wolf2019-06-202-3/+3
* | | | | | | Fix typoClifford Wolf2019-06-201-2/+2
* | | | | | | Merge branch 'towoe-unpacked_arrays'Clifford Wolf2019-06-202-1/+23
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| * | | | | | Add proper test for SV-style arraysClifford Wolf2019-06-203-6/+16
| * | | | | | Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into towo...Clifford Wolf2019-06-203-1/+13
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| * | | | | | Unpacked array declaration using sizeTobias Wölfel2019-06-193-1/+13
* | | | | | | Merge pull request #1111 from acw1251/help_summary_fixesEddie Hung2019-06-194-6/+6
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| * | | | | | | Fixed small typo in ice40_unlut help summaryacw12512019-06-191-1/+1
| * | | | | | | Fixed the help summary line for a few commandsacw12512019-06-194-6/+6
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* | | | | | | Fix bug in #1078, add entry to CHANGELOGEddie Hung2019-06-192-3/+4
* | | | | | | Merge pull request #1109 from YosysHQ/clifford/fix1106Clifford Wolf2019-06-196-9/+48
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| * | | | | | | Add "read_verilog -pwires" feature, closes #1106Clifford Wolf2019-06-196-9/+48
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* | | | | | | Merge pull request #1105 from YosysHQ/clifford/fixlogicinitClifford Wolf2019-06-195-16/+92
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| * | | | | | | Add defvalue test, minor autotest fixes for .sv filesClifford Wolf2019-06-192-14/+37
| * | | | | | | Use input default values in hierarchy passClifford Wolf2019-06-191-0/+38
| * | | | | | | Add defaultvalue attributeClifford Wolf2019-06-192-0/+15
| * | | | | | | Fix handling of "logic" variables with initial valueClifford Wolf2019-06-191-2/+2
* | | | | | | | Make tests/aiger less chattyClifford Wolf2019-06-191-4/+6
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* | | | | | | Merge pull request #1100 from bwidawsk/homeClifford Wolf2019-06-195-0/+8
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| * | | | | | | Support filename rewrite in backendsBen Widawsky2019-06-184-0/+4
| * | | | | | | Support ~ for home directoryBen Widawsky2019-06-181-0/+4
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* | | | | | | Merge pull request #1104 from whitequark/case-semanticsClifford Wolf2019-06-192-1/+40
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| * | | | | | Explain exact semantics of switch and case rules in the manual.whitequark2019-06-191-0/+12
| * | | | | | In RTLIL::Module::check(), check process invariants.whitequark2019-06-191-1/+28
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* | | | | | Merge pull request #1086 from udif/pr_elab_sys_tasks2Clifford Wolf2019-06-182-3/+13
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| * | | | | Fixed brojen $error()/$info/$warning() on non-generate blocksUdi Finkelstein2019-06-112-3/+13
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* | | | | Add timescale and generated-by header to yosys-smtbmc MkVcdClifford Wolf2019-06-161-0/+2
* | | | | Merge pull request #829 from abdelrahmanhosny/masterSerge Bazanski2019-06-132-0/+46
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| * | | | address review commentsAbdelrahman2019-03-011-23/+9
| * | | | add dockerignore fileAbdelrahman2019-02-261-0/+13
| * | | | dockerize yosysAbdelrahman2019-02-261-0/+47
* | | | | Add some more commentsEddie Hung2019-06-101-1/+6
* | | | | Merge pull request #1082 from corecode/u4kDavid Shah2019-06-101-0/+24
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| * | | | | ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4kSimon Schubert2019-06-101-0/+24
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