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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 10:04:42 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 10:13:52 -0700 |
| commit | 0221f3e1c5b427678c5679027ee47ec7c0b8321d (patch) | |
| tree | 0a2993c425f40f1b44e1b2bcab521b73631729aa | |
| parent | 477e566e8d203ec7754c90fc845d7f3f759f2974 (diff) | |
| download | yosys-0221f3e1c5b427678c5679027ee47ec7c0b8321d.tar.gz yosys-0221f3e1c5b427678c5679027ee47ec7c0b8321d.tar.bz2 yosys-0221f3e1c5b427678c5679027ee47ec7c0b8321d.zip | |
Fix sign extension when sign is 1'bx
| -rw-r--r-- | kernel/rtlil.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index a09f4a0d1..95a24c93f 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3437,7 +3437,7 @@ void RTLIL::SigSpec::extend_u0(int width, bool is_signed) if (width_ < width) { RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx; - if (!is_signed) + if (padding != RTLIL::State::Sx && !is_signed) padding = RTLIL::State::S0; while (width_ < width) append(padding); |