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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 12:40:05 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 12:40:05 -0700 |
| commit | e33cbb0dde72b292002a9fc7158857b19803effe (patch) | |
| tree | 408111f640ee7dffe4c875b05c0996879beab040 | |
| parent | b77322034c9234a8c24c6f53ed028fe29737b6b4 (diff) | |
| download | yosys-e33cbb0dde72b292002a9fc7158857b19803effe.tar.gz yosys-e33cbb0dde72b292002a9fc7158857b19803effe.tar.bz2 yosys-e33cbb0dde72b292002a9fc7158857b19803effe.zip | |
Revert "Fix sign extension when sign is 1'bx"
This reverts commit 0221f3e1c5b427678c5679027ee47ec7c0b8321d.
| -rw-r--r-- | kernel/rtlil.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 95a24c93f..a09f4a0d1 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3437,7 +3437,7 @@ void RTLIL::SigSpec::extend_u0(int width, bool is_signed) if (width_ < width) { RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx; - if (padding != RTLIL::State::Sx && !is_signed) + if (!is_signed) padding = RTLIL::State::S0; while (width_ < width) append(padding); |