| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Merge pull request #1085 from YosysHQ/eddie/shregmap_improve | Eddie Hung | 2019-06-21 | 3 | -3/+129 |
| |\ | | | | | Improve shregmap to handle case where first flop is common to two chains | ||||
| | * | Actually, there might not be any harm in updating sigmap... | Eddie Hung | 2019-06-20 | 1 | -3/+1 |
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| | * | Add comment as per @cliffordwolf | Eddie Hung | 2019-06-20 | 1 | -0/+11 |
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| | * | Add shregmap -tech xilinx test | Eddie Hung | 2019-06-12 | 2 | -2/+63 |
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| | * | Revert "Try way that doesn't involve creating a new wire" | Eddie Hung | 2019-06-11 | 1 | -15/+10 |
| | | | | | | | | | This reverts commit 2f427acc9ed23c77e89386f4fbf53ac580bf0f0b. | ||||
| | * | Try way that doesn't involve creating a new wire | Eddie Hung | 2019-06-11 | 1 | -10/+15 |
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| | * | If d_bit already in sigbit_chain_next, create extra wire | Eddie Hung | 2019-06-10 | 1 | -3/+6 |
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| | * | Add test | Eddie Hung | 2019-06-10 | 2 | -0/+53 |
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| * | | Merge pull request #1122 from YosysHQ/clifford/jsonports | Clifford Wolf | 2019-06-21 | 2 | -0/+16 |
| |\ \ | | | | | | | Added JSON upto and offset | ||||
| | * | | Added JSON upto and offset | Clifford Wolf | 2019-06-21 | 2 | -0/+16 |
| |/ / | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Merge pull request #1121 from YosysHQ/ecp5-ccu2c-inv | Clifford Wolf | 2019-06-21 | 1 | -4/+5 |
| |\ \ | | | | | | | ecp5: Improve mapping of $alu when BI is used | ||||
| | * | | ecp5: Improve mapping of $alu when BI is used | David Shah | 2019-06-21 | 1 | -4/+5 |
| |/ / | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | Merge pull request #1117 from bwidawsk/more-home | Clifford Wolf | 2019-06-21 | 2 | -0/+5 |
| |\ \ | | | | | | | Add a few more filename rewrites | ||||
| | * | | Add a few more filename rewrites | Ben Widawsky | 2019-06-20 | 2 | -0/+5 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This now allows a full pipeline to work, something such as: yosys -p "synth_ecp5 -json ~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v" Otherwise, you will get something along the lines of: ERROR: Can't open output file `~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v' for writing: No such file or directory Signed-off-by: Ben Widawsky <ben@bwidawsk.net> | ||||
| * | | | Merge pull request #1119 from YosysHQ/eddie/fix1118 | Clifford Wolf | 2019-06-21 | 2 | -0/+12 |
| |\ \ \ | | | | | | | | | Make genvar a signed type | ||||
| | * | | | Add test | Eddie Hung | 2019-06-20 | 1 | -0/+11 |
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| | * | | | Make genvar a signed type | Eddie Hung | 2019-06-20 | 1 | -0/+1 |
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| * | | | | Merge pull request #1116 from YosysHQ/eddie/fix1115 | Clifford Wolf | 2019-06-21 | 3 | -7/+41 |
| |\ \ \ \ | | | | | | | | | | | Sign extend unsized 'bx and 'bz values | ||||
| | * | | | | Add CHANGELOG entry | Eddie Hung | 2019-06-20 | 1 | -1/+2 |
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| | * | | | | Extend sign extension tests | Eddie Hung | 2019-06-20 | 1 | -4/+16 |
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| | * | | | | Maintain "is_unsized" state of constants | Eddie Hung | 2019-06-20 | 1 | -6/+6 |
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| | * | | | | Revert "Fix sign extension when sign is 1'bx" | Eddie Hung | 2019-06-20 | 1 | -1/+1 |
| | | | | | | | | | | | | | | | | | | | | | This reverts commit 0221f3e1c5b427678c5679027ee47ec7c0b8321d. | ||||
| | * | | | | Remove leftover comment | Eddie Hung | 2019-06-20 | 1 | -3/+0 |
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| | * | | | | Add test | Eddie Hung | 2019-06-20 | 1 | -0/+24 |
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| | * | | | | Fix sign extension when sign is 1'bx | Eddie Hung | 2019-06-20 | 1 | -1/+1 |
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| * / / / | Fix gcc invalidation behaviour for write_aiger | Eddie Hung | 2019-06-20 | 1 | -1/+2 |
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| * | | | Fix typo, fixes #1095 | Clifford Wolf | 2019-06-20 | 1 | -1/+1 |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | Improve shregmap help message, fixes #1113 | Clifford Wolf | 2019-06-20 | 1 | -0/+2 |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | Update some .gitignore files | Clifford Wolf | 2019-06-20 | 2 | -3/+3 |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | Fix typo | Clifford Wolf | 2019-06-20 | 1 | -2/+2 |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | Merge branch 'towoe-unpacked_arrays' | Clifford Wolf | 2019-06-20 | 2 | -1/+23 |
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| | * | | Add proper test for SV-style arrays | Clifford Wolf | 2019-06-20 | 3 | -6/+16 |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into ↵ | Clifford Wolf | 2019-06-20 | 3 | -1/+13 |
| |/| | | | | | | | | | | | towoe-unpacked_arrays | ||||
| | * | | Unpacked array declaration using size | Tobias Wölfel | 2019-06-19 | 3 | -1/+13 |
| | | | | | | | | | | | | | | | | | | | | | | | | | Allows fixed-sized array dimension specified by a single number. This commit is based on the work from PeterCrozier https://github.com/YosysHQ/yosys/pull/560. But is split out of the original work. | ||||
| * | | | Merge pull request #1111 from acw1251/help_summary_fixes | Eddie Hung | 2019-06-19 | 4 | -6/+6 |
| |\ \ \ | | | | | | | | | Fixed the help summary line for a few commands | ||||
| | * | | | Fixed small typo in ice40_unlut help summary | acw1251 | 2019-06-19 | 1 | -1/+1 |
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| | * | | | Fixed the help summary line for a few commands | acw1251 | 2019-06-19 | 4 | -6/+6 |
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| * | | | Fix bug in #1078, add entry to CHANGELOG | Eddie Hung | 2019-06-19 | 2 | -3/+4 |
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| * | | | Merge pull request #1109 from YosysHQ/clifford/fix1106 | Clifford Wolf | 2019-06-19 | 6 | -9/+48 |
| |\ \ \ | | | | | | | | | Add "read_verilog -pwires" feature | ||||
| | * | | | Add "read_verilog -pwires" feature, closes #1106 | Clifford Wolf | 2019-06-19 | 6 | -9/+48 |
| |/ / / | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | Merge pull request #1105 from YosysHQ/clifford/fixlogicinit | Clifford Wolf | 2019-06-19 | 5 | -16/+92 |
| |\ \ \ | | | | | | | | | Improve handling of initial/default values | ||||
| | * | | | Add defvalue test, minor autotest fixes for .sv files | Clifford Wolf | 2019-06-19 | 2 | -14/+37 |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | | Use input default values in hierarchy pass | Clifford Wolf | 2019-06-19 | 1 | -0/+38 |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | | Add defaultvalue attribute | Clifford Wolf | 2019-06-19 | 2 | -0/+15 |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | | Fix handling of "logic" variables with initial value | Clifford Wolf | 2019-06-19 | 1 | -2/+2 |
| | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | | Make tests/aiger less chatty | Clifford Wolf | 2019-06-19 | 1 | -4/+6 |
| |/ / / | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | Merge pull request #1100 from bwidawsk/home | Clifford Wolf | 2019-06-19 | 5 | -0/+8 |
| |\ \ \ | | | | | | | | | Support ~ in filename parsing | ||||
| | * | | | Support filename rewrite in backends | Ben Widawsky | 2019-06-18 | 4 | -0/+4 |
| | | | | | | | | | | | | | | | | | Signed-off-by: Ben Widawsky <ben@bwidawsk.net> | ||||
| | * | | | Support ~ for home directory | Ben Widawsky | 2019-06-18 | 1 | -0/+4 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is tested on Linux only v2: Wrap functioanlity in ifndef _WIN32 (eddiehung) Find '~/' instead of '~' (cliffordwolf) Signed-off-by: Ben Widawsky <ben@bwidawsk.net> | ||||
| * | | | | Merge pull request #1104 from whitequark/case-semantics | Clifford Wolf | 2019-06-19 | 2 | -1/+40 |
| |\ \ \ \ | |/ / / |/| | | | Clarify switch/case semantics in RTLIL | ||||
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