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* Fixed bug where GP_COUNTx_ADV would wrap even when KEEP was highAndrew Zonenberg2017-08-151-47/+47
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* Merge branch 'azonenberg-rmports'Clifford Wolf2017-08-152-0/+188
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| * Mostly coding style related fixes in rmports passClifford Wolf2017-08-151-30/+33
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| * Merge branch 'rmports' of https://github.com/azonenberg/yosys into ↵Clifford Wolf2017-08-152-0/+185
|/| | | | | | | azonenberg-rmports
| * rmports: Now remove ports from cell instances if we optimized them out of ↵Andrew Zonenberg2017-08-141-2/+35
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| * ProcessModule is no longer virtual (why was it in the first place?)Andrew Zonenberg2017-08-141-1/+1
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| * rmports now works on all modules in the design, not just the top.Andrew Zonenberg2017-08-141-4/+7
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| * Updated Makefile to reflect opt_rmports being renamed to rmportsAndrew Zonenberg2017-08-141-1/+1
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| * Renamed opt_rmports pass to rmportsAndrew Zonenberg2017-08-141-5/+5
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| * Improved handling of constant connections in opt_rmportsAndrew Zonenberg2017-08-141-0/+2
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| * Fixed handling of cell ports that aren't wiresAndrew Zonenberg2017-08-141-0/+3
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| * opt_rmports: Fixed incorrect handling of multi-bit netsAndrew Zonenberg2017-08-141-12/+27
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| * Removed commented out debug codeAndrew Zonenberg2017-08-141-4/+0
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| * Added opt_rmports pass (remove unconnected ports from top-level modules)Andrew Zonenberg2017-08-142-0/+133
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* | Merge pull request #381 from azonenberg/countfixClifford Wolf2017-08-144-504/+900
|\ \ | | | | | | Added better behavioral models for GreenPAK counters. Refactored cells_sim into two files so analog/mixed signal stuff is separate
| * | Fixed typo in GP_COUNT8 sim modelAndrew Zonenberg2017-08-141-1/+1
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| * | Fixed typo in error messageAndrew Zonenberg2017-08-141-1/+1
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| * | Changed LEVEL resets for GP_COUNTx to be properly synthesizeableAndrew Zonenberg2017-08-141-48/+60
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| * | Changed LEVEL resets to be edge triggered anywayAndrew Zonenberg2017-08-141-4/+4
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| * | Added level-triggered reset support to GP_COUNTx simulation modelsAndrew Zonenberg2017-08-141-2/+68
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| * | Fixed undeclared "count" in GP_COUNT8_ADVAndrew Zonenberg2017-08-141-0/+2
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| * | Fixed undeclared "count" in GP_COUNT14_ADVAndrew Zonenberg2017-08-141-0/+2
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| * | Fixed typo in last commitAndrew Zonenberg2017-08-141-3/+3
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| * | Finished initial GP_COUNT8/14/8_ADV/14_ADV sim models. Don't support clock ↵Andrew Zonenberg2017-08-142-37/+293
| | | | | | | | | | | | divide, but do everything else.
| * | Fixed typo in COUNT8 modelAndrew Zonenberg2017-08-141-2/+2
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| * | Moved GP_POR out of digital cells b/c it has delaysAndrew Zonenberg2017-08-142-21/+21
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| * | Improved cells_sim_digital model for GP_COUNT8Andrew Zonenberg2017-08-142-40/+75
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| * | Refactored GreenPAK4 cells_sim into cells_sim_ams and cells_sim_digitalAndrew Zonenberg2017-08-144-428/+451
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* | Merge pull request #383 from azonenberg/abcfnamesClifford Wolf2017-08-141-0/+3
|\ \ | | | | | | abc: Allow +/ filenames in the abc command
| * | abc: Allow +/ filenames in the abc commandRobert Ou2017-08-141-0/+3
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* | Merge pull request #382 from azonenberg/jsoniofixClifford Wolf2017-08-141-0/+1
|\ \ | | | | | | json: Parse inout correctly rather than as an output
| * | json: Parse inout correctly rather than as an outputRobert Ou2017-08-141-0/+1
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* | Merge pull request #384 from azonenberg/crtechlibClifford Wolf2017-08-141-2/+66
|\ \ | |/ |/| CoolRunner-II technology library improvements
| * coolrunner2: Add INVERT parameter to some BUFGsRobert Ou2017-08-141-2/+6
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| * coolrunner2: Add FFs with clock enable to cells_sim.vRobert Ou2017-08-141-0/+60
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* Add support for set-reset cell variants to opt_rmdffClifford Wolf2017-08-091-0/+182
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* Auto-detect JSON front-endClifford Wolf2017-08-091-0/+2
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* Add handling of constant reset signals to opt_rmdffClifford Wolf2017-08-061-1/+23
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* Add "yosys-smtbmc --smtc-init --smtc-top --noinit"Clifford Wolf2017-08-041-20/+66
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* Add "-undefined dynamic_lookup" to OSX "yosys-config --ldflags"Clifford Wolf2017-08-041-1/+5
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* Fix typo in "abc" pass help messageClifford Wolf2017-07-291-1/+1
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* Add merging of "past FFs" to verific importerClifford Wolf2017-07-291-2/+76
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* Add consolidation of init attributes to opt_clean, some opt_clean log fixesClifford Wolf2017-07-291-6/+82
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* Add minimal support for PSL in VHDL via VerificClifford Wolf2017-07-281-19/+155
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* Add simple VHDL+PSL exampleClifford Wolf2017-07-284-17/+64
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* Improve Verific HDL language optionsClifford Wolf2017-07-281-4/+4
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* Fix handling of non-user-declared Verific netbusClifford Wolf2017-07-281-2/+3
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* Improve Verific SVA importerClifford Wolf2017-07-272-7/+42
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* Add counter.sv SVA testClifford Wolf2017-07-271-0/+29
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* Add log_warning_noprefix() API, Use for Verific warnings and errorsClifford Wolf2017-07-273-1/+37
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