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| author | Robert Ou <rqou@robertou.com> | 2017-08-07 04:01:18 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-08-14 12:13:33 -0700 |
| commit | 78fd24f40f1e2be64e8ea8116a8a2277cb3a9baf (patch) | |
| tree | b6b617bacfa371010fce3d790a76229043243abb | |
| parent | 1e3ffd57cbfce0ec6f1bdd4f2dd20d18e0855c57 (diff) | |
| download | yosys-78fd24f40f1e2be64e8ea8116a8a2277cb3a9baf.tar.gz yosys-78fd24f40f1e2be64e8ea8116a8a2277cb3a9baf.tar.bz2 yosys-78fd24f40f1e2be64e8ea8116a8a2277cb3a9baf.zip | |
coolrunner2: Add INVERT parameter to some BUFGs
| -rw-r--r-- | techlibs/coolrunner2/cells_sim.v | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/techlibs/coolrunner2/cells_sim.v b/techlibs/coolrunner2/cells_sim.v index d8dca1922..562fb1efd 100644 --- a/techlibs/coolrunner2/cells_sim.v +++ b/techlibs/coolrunner2/cells_sim.v @@ -143,17 +143,21 @@ module BUFG(I, O); endmodule module BUFGSR(I, O); + parameter INVERT = 0; + input I; output O; - assign O = I; + assign O = INVERT ? ~I : I; endmodule module BUFGTS(I, O); + parameter INVERT = 0; + input I; output O; - assign O = I; + assign O = INVERT ? ~I : I; endmodule module FDDCP (C, PRE, CLR, D, Q); |