iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Fixed bug where GP_COUNTx_ADV would wrap even when KEEP was high	Andrew Zonenberg	2017-08-15	1	-47/+47
*	Merge branch 'azonenberg-rmports'	Clifford Wolf	2017-08-15	2	-0/+188
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\| *	Mostly coding style related fixes in rmports pass	Clifford Wolf	2017-08-15	1	-30/+33
\| *	Merge branch 'rmports' of https://github.com/azonenberg/yosys into azonenberg...	Clifford Wolf	2017-08-15	2	-0/+185
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\| *	rmports: Now remove ports from cell instances if we optimized them out of tha...	Andrew Zonenberg	2017-08-14	1	-2/+35
\| *	ProcessModule is no longer virtual (why was it in the first place?)	Andrew Zonenberg	2017-08-14	1	-1/+1
\| *	rmports now works on all modules in the design, not just the top.	Andrew Zonenberg	2017-08-14	1	-4/+7
\| *	Updated Makefile to reflect opt_rmports being renamed to rmports	Andrew Zonenberg	2017-08-14	1	-1/+1
\| *	Renamed opt_rmports pass to rmports	Andrew Zonenberg	2017-08-14	1	-5/+5
\| *	Improved handling of constant connections in opt_rmports	Andrew Zonenberg	2017-08-14	1	-0/+2
\| *	Fixed handling of cell ports that aren't wires	Andrew Zonenberg	2017-08-14	1	-0/+3
\| *	opt_rmports: Fixed incorrect handling of multi-bit nets	Andrew Zonenberg	2017-08-14	1	-12/+27
\| *	Removed commented out debug code	Andrew Zonenberg	2017-08-14	1	-4/+0
\| *	Added opt_rmports pass (remove unconnected ports from top-level modules)	Andrew Zonenberg	2017-08-14	2	-0/+133
* \|	Merge pull request #381 from azonenberg/countfix	Clifford Wolf	2017-08-14	4	-504/+900
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\| * \|	Fixed typo in GP_COUNT8 sim model	Andrew Zonenberg	2017-08-14	1	-1/+1
\| * \|	Fixed typo in error message	Andrew Zonenberg	2017-08-14	1	-1/+1
\| * \|	Changed LEVEL resets for GP_COUNTx to be properly synthesizeable	Andrew Zonenberg	2017-08-14	1	-48/+60
\| * \|	Changed LEVEL resets to be edge triggered anyway	Andrew Zonenberg	2017-08-14	1	-4/+4
\| * \|	Added level-triggered reset support to GP_COUNTx simulation models	Andrew Zonenberg	2017-08-14	1	-2/+68
\| * \|	Fixed undeclared "count" in GP_COUNT8_ADV	Andrew Zonenberg	2017-08-14	1	-0/+2
\| * \|	Fixed undeclared "count" in GP_COUNT14_ADV	Andrew Zonenberg	2017-08-14	1	-0/+2
\| * \|	Fixed typo in last commit	Andrew Zonenberg	2017-08-14	1	-3/+3
\| * \|	Finished initial GP_COUNT8/14/8_ADV/14_ADV sim models. Don't support clock di...	Andrew Zonenberg	2017-08-14	2	-37/+293
\| * \|	Fixed typo in COUNT8 model	Andrew Zonenberg	2017-08-14	1	-2/+2
\| * \|	Moved GP_POR out of digital cells b/c it has delays	Andrew Zonenberg	2017-08-14	2	-21/+21
\| * \|	Improved cells_sim_digital model for GP_COUNT8	Andrew Zonenberg	2017-08-14	2	-40/+75
\| * \|	Refactored GreenPAK4 cells_sim into cells_sim_ams and cells_sim_digital	Andrew Zonenberg	2017-08-14	4	-428/+451
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* \|	Merge pull request #383 from azonenberg/abcfnames	Clifford Wolf	2017-08-14	1	-0/+3
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\| * \|	abc: Allow +/ filenames in the abc command	Robert Ou	2017-08-14	1	-0/+3
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* \|	Merge pull request #382 from azonenberg/jsoniofix	Clifford Wolf	2017-08-14	1	-0/+1
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\| * \|	json: Parse inout correctly rather than as an output	Robert Ou	2017-08-14	1	-0/+1
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* \|	Merge pull request #384 from azonenberg/crtechlib	Clifford Wolf	2017-08-14	1	-2/+66
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\| *	coolrunner2: Add INVERT parameter to some BUFGs	Robert Ou	2017-08-14	1	-2/+6
\| *	coolrunner2: Add FFs with clock enable to cells_sim.v	Robert Ou	2017-08-14	1	-0/+60
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*	Add support for set-reset cell variants to opt_rmdff	Clifford Wolf	2017-08-09	1	-0/+182
*	Auto-detect JSON front-end	Clifford Wolf	2017-08-09	1	-0/+2
*	Add handling of constant reset signals to opt_rmdff	Clifford Wolf	2017-08-06	1	-1/+23
*	Add "yosys-smtbmc --smtc-init --smtc-top --noinit"	Clifford Wolf	2017-08-04	1	-20/+66
*	Add "-undefined dynamic_lookup" to OSX "yosys-config --ldflags"	Clifford Wolf	2017-08-04	1	-1/+5
*	Fix typo in "abc" pass help message	Clifford Wolf	2017-07-29	1	-1/+1
*	Add merging of "past FFs" to verific importer	Clifford Wolf	2017-07-29	1	-2/+76
*	Add consolidation of init attributes to opt_clean, some opt_clean log fixes	Clifford Wolf	2017-07-29	1	-6/+82
*	Add minimal support for PSL in VHDL via Verific	Clifford Wolf	2017-07-28	1	-19/+155
*	Add simple VHDL+PSL example	Clifford Wolf	2017-07-28	4	-17/+64
*	Improve Verific HDL language options	Clifford Wolf	2017-07-28	1	-4/+4
*	Fix handling of non-user-declared Verific netbus	Clifford Wolf	2017-07-28	1	-2/+3
*	Improve Verific SVA importer	Clifford Wolf	2017-07-27	2	-7/+42
*	Add counter.sv SVA test	Clifford Wolf	2017-07-27	1	-0/+29
*	Add log_warning_noprefix() API, Use for Verific warnings and errors	Clifford Wolf	2017-07-27	3	-1/+37