aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* ast: delete wires and localparams after finishing const evaluationXiretza2021-06-141-0/+8
|
* verilog: fix leaking ASTNodesXiretza2021-06-142-7/+15
|
* ast: fix error condition causing assert to failXiretza2021-06-141-2/+1
| | | | | type2str returns a string that doesn't start with $ or \, so it can't be assigned to an IdString.
* macos: fix leak in proc_self_dirname()Zachary Snow2021-06-141-1/+3
|
* Simplify some RTLIL destructorsRupert Swarbrick2021-06-141-10/+10
| | | | | No change in behaviour, but use range-based for loops instead of iterators.
* verilog: Squash a memory leak.Marcelina Kościelnicka2021-06-144-19/+14
| | | | That was added in ecc22f7fedfa639482dbc55a05709da85116a60f
* Add regression test for #2824.Marcelina Kościelnicka2021-06-111-0/+7
|
* opt_muxtree: Update port_off and port_idx even for constant bitsgatecat2021-06-111-17/+16
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* opt_expr: Fix mul/div/mod by POT patterns to support >= 32 bits.Marcelina Kościelnicka2021-06-093-122/+120
| | | | | The previous code, in addition to being needlessly limitted to 32 bits in the first place, also had UB for the 31th bit (doing 1 << 31).
* opt_expr: Optimize div/mod by const 1.Marcelina Kościelnicka2021-06-091-4/+4
| | | | | | | | Turns out the code for div by a power of 2 is already almost capable of optimizing this to a shift-by-0 or and-with-0, which will be further folded into nothingness; let's beef it up to handle div by 1 as well. Fixes #2820.
* Merge pull request #2817 from YosysHQ/claire/fixemailsClaire Xen2021-06-09325-1308/+1311
|\ | | | | Fixing old e-mail addresses and deadnames
| * Fix deadname SVN linksClaire Xenia Wolf2021-06-092-3/+3
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| * Intersynth URLClaire Xenia Wolf2021-06-092-2/+2
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| * More deadname stuffClaire Xenia Wolf2021-06-092-4/+4
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| * Fix icestorm linksClaire Xenia Wolf2021-06-092-516/+516
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| * More deadname stuffClaire Xenia Wolf2021-06-0910-27/+27
| |
| * Use HTTPS for website links, gatecat emailClaire Xenia Wolf2021-06-0920-26/+26
| | | | | | | | | | | | | | | | | | | | git ls-tree -r --name-only HEAD | xargs sed -i -rf ~/fixemails.sed s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+(Shah|gatecat)\s+<(dave|david|gatecat)@(symbioticeda.com|yosyshq.com|ds0.me)>/gatecat <gatecat@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/|http://yosyshq.net/yosys/,https://yosyshq.net/yosys/,g;
| * Fix files with CRLF line endingsClaire Xenia Wolf2021-06-095-422/+422
| |
| * Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-08309-331/+330
| | | | | | | | | | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
| * Add claire deadname stuff to .mailmapClaire Xenia Wolf2021-06-081-0/+4
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | verilog: check for module scope identifiers during width detectionZachary Snow2021-06-084-13/+41
| | | | | | | | | | | | | | | | The recent fix for case expression width detection causes the width of the expressions to be queried before they are simplified. Because the logic supporting module scope identifiers only existed in simplify, looking them up would fail during width detection. This moves the logic to a common helper used in both simplify() and detectSignWidthWorker().
* | mem2reg: tolerate out of bounds constant accessesZachary Snow2021-06-084-5/+94
| | | | | | | | This brings the mem2reg behavior in line with the nomem2reg behavior.
* | autoname: simple perf optimizationsZachary Snow2021-06-081-11/+15
|/
* sv: support tasks and functions within packagesZachary Snow2021-06-015-2/+56
|
* kernel/mem: Recognize some deprecated memory port configs.Marcelina Kościelnicka2021-06-011-0/+10
| | | | | | | | | | Transparency is meaningless for asynchronous ports, so we assume transparent == false to simplify the code in this case. Likewise, enable is meaningless, and we assume it is const-1. However, turns out that nMigen emits the former, and Verilog frontend emits the latter, so squash these issues when ingesting a $memrd cell. Fixes #2811.
* memory_map: Improve start_offset handling.Marcelina Kościelnicka2021-05-312-35/+131
| | | | Fixes #2775.
* memory_share: Add read port merging.Marcelina Kościelnicka2021-05-291-0/+140
| | | | | This is mostly meant for wide port recognition, but may also happen to merge some ports with compatible initial/reset values (eg. 0 vs x).
* memory_share: Improve sat-based port sharing.Marcelina Kościelnicka2021-05-281-117/+151
|
* Make a few passes auto-call Mem::narrow instead of rejecting wide ports.Marcelina Kościelnicka2021-05-285-33/+10
| | | | | | This essentially adds wide port support for free in passes that don't have a usefully better way of handling wide ports than just breaking them up to narrow ports, avoiding "please run memory_narrow" annoyance.
* backends/verilog: Add support for memory read port reset and init value.Marcelina Kościelnicka2021-05-271-9/+81
|
* backends/verilog: Add wide port support.Marcelina Kościelnicka2021-05-271-43/+88
|
* memory_share: Improve same-address merging, recognize wide write ports.Marcelina Kościelnicka2021-05-271-204/+77
|
* kernel/mem: Add helpers for write port widening.Marcelina Kościelnicka2021-05-272-0/+57
|
* kernel/mem: Add sub_addr helpers.Marcelina Kościelnicka2021-05-263-26/+32
|
* kernel/mem: Add prepare_wr_merge helper.Marcelina Kościelnicka2021-05-262-0/+27
|
* backends/verilog: Try to preserve mem write port priorities.Marcelina Kościelnicka2021-05-261-32/+84
|
* mem/extract_rdff: Fix "no FF made" edge case.Marcelina Kościelnicka2021-05-252-3/+9
| | | | | | | When converting a sync transparent read port with const address to async read port, nothing at all needs to be done other than clk_enable change, and thus we have no FF cell to return. Handle this case correctly in the helper and in its users.
* memory_bram: Reuse extract_rdff helper for make_outreg.Marcelina Kościelnicka2021-05-255-40/+52
| | | | | Also properly skip read ports with init value or reset when not making use of make_outreg. Proper support for matching those will land later.
* verilog: fix case expression sign and width handlingZachary Snow2021-05-255-12/+157
| | | | | | | | | - The case expression and case item expressions are extended to the maximum width among them, and are only interpreted as signed if all of them are signed - Add overall width and sign detection for AST_CASE - Add sign argument to genWidthRTLIL helper - Coverage for both const and non-const case statements
* sv: support remaining assignment operatorsZachary Snow2021-05-253-42/+64
| | | | | - Add support for: *=, /=, %=, <<=, >>=, <<<=, >>>= - Unify existing support for: +=, -=, &=, |=, ^=
* mem/extract_rdff: Add alternate transparency handling.Marcelina Kościelnicka2021-05-251-18/+80
| | | | | | | | | | When extracting read register from a transparent port that has an enable, reset, or initial value, the usual trick of putting a register on the address instead of data doesn't work. In this case, create soft transparency logic instead. When transparency masks land, this will also be used to handle ports that are transparent to only a subset of write ports.
* opt_mem: Add reset/init value support.Marcelina Kościelnicka2021-05-251-0/+12
|
* kernel/mem: Add model support for read port init value and resets.Marcelina Kościelnicka2021-05-252-4/+73
| | | | | | | Like wide port support, this is still completely unusable, and support in various passes will be gradually added later. It also has no support at all in the cell library, so attempting to create a read port with a reset or initial value will cause an assert failure for now.
* mem/extract_rdff: Fix wire naming and wide port support.Marcelina Kościelnicka2021-05-251-6/+22
|
* memory_bram: Respect write port priority.Marcelina Kościelnicka2021-05-251-0/+14
|
* opt_mem_feedback: Respect write port priority.Marcelina Kościelnicka2021-05-252-0/+62
|
* kernel/mem: Add emulate_priority helper.Marcelina Kościelnicka2021-05-252-0/+44
|
* Add memory_narrow pass.Marcelina Kościelnicka2021-05-252-0/+68
|
* memory_share: Add wide port support.Marcelina Kościelnicka2021-05-251-0/+6
|
* opt_mem_feedback: Add wide port support.Marcelina Kościelnicka2021-05-251-14/+24
|
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-24 10:54:27 +0000