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| author | Claire Xenia Wolf <claire@clairexen.net> | 2021-06-09 12:42:52 +0200 |
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| committer | Claire Xenia Wolf <claire@clairexen.net> | 2021-06-09 12:42:52 +0200 |
| commit | 2d95a7da9cd2e8cf1854215241c5df7d67ca0c1e (patch) | |
| tree | 937aab80e1f59ee791386d7d5e5a4fb3f9c73bca | |
| parent | 0ff4fb1eb35bfba5b7a936401b58deb21776c81a (diff) | |
| download | yosys-2d95a7da9cd2e8cf1854215241c5df7d67ca0c1e.tar.gz yosys-2d95a7da9cd2e8cf1854215241c5df7d67ca0c1e.tar.bz2 yosys-2d95a7da9cd2e8cf1854215241c5df7d67ca0c1e.zip | |
Intersynth URL
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| -rw-r--r-- | backends/intersynth/intersynth.cc | 2 | ||||
| -rw-r--r-- | manual/command-reference-manual.tex | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index 758a8792b..59173c4a2 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -68,7 +68,7 @@ struct IntersynthBackend : public Backend { log(" only write selected modules. modules must be selected entirely or\n"); log(" not at all.\n"); log("\n"); - log("http://www.clifford.at/intersynth/\n"); + log("http://bygone.clairexen.net/intersynth/\n"); log("\n"); } void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override diff --git a/manual/command-reference-manual.tex b/manual/command-reference-manual.tex index a3264b4cd..960078cc7 100644 --- a/manual/command-reference-manual.tex +++ b/manual/command-reference-manual.tex @@ -6999,7 +6999,7 @@ a tool for Coarse-Grain Example-Driven Interconnect Synthesis. only write selected modules. modules must be selected entirely or not at all. -http://www.clifford.at/intersynth/ +http://bygone.clairexen.net/intersynth/ \end{lstlisting} \section{write\_json -- write design to a JSON file} |