| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
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| * | | | Refactor common parts of SAT-using optimizations into a helper. | Marcelina Kościelnicka | 2021-08-09 | 7 | -153/+224 | |
| * | | | Bump version | github-actions[bot] | 2021-08-08 | 1 | -1/+1 | |
| * | | | opt_merge: Use FfInitVals. | Marcelina Kościelnicka | 2021-08-08 | 3 | -28/+51 | |
| * | | | Bump version | github-actions[bot] | 2021-08-07 | 1 | -1/+1 | |
| * | | | verilog: Support tri/triand/trior wire types. | Marcelina Kościelnicka | 2021-08-06 | 1 | -0/+3 | |
| * | | | Bump version | github-actions[bot] | 2021-08-05 | 1 | -1/+1 | |
| * | | | memory_share: Don't skip ports with EN wired to input for SAT sharing. | Marcelina Kościelnicka | 2021-08-04 | 1 | -3/+1 | |
| * | | | Bump version | github-actions[bot] | 2021-08-04 | 1 | -1/+1 | |
| * | | | memory_bram: Move init data swizzling before other swizzling. | Marcelina Kościelnicka | 2021-08-03 | 1 | -18/+18 | |
| * | | | Bump version | github-actions[bot] | 2021-08-03 | 1 | -1/+1 | |
| * | | | Require latest verific | Miodrag Milanovic | 2021-08-02 | 1 | -1/+1 | |
| * | | | Bump version | github-actions[bot] | 2021-08-02 | 1 | -1/+1 | |
| * | | | backend/verilog: Add alternate mode for transparent read port output. | Marcelina Kościelnicka | 2021-08-01 | 1 | -1/+71 | |
| * | | | memory_bram: Some refactoring | Marcelina Kościelnicka | 2021-08-01 | 1 | -196/+174 | |
| * | | | Bump version | github-actions[bot] | 2021-07-31 | 1 | -1/+1 | |
| * | | | Update version.yml | Miodrag Milanović | 2021-07-30 | 1 | -2/+5 | |
| * | | | Fixes xc7 BRAM36s | Maciej Dudek | 2021-07-30 | 1 | -4/+6 | |
| * | | | proc_rmdead: use explicit pattern set when there are no wildcards | Zachary Snow | 2021-07-29 | 4 | -2/+386 | |
| * | | | genrtlil: add width detection for AST_PREFIX nodes | Zachary Snow | 2021-07-29 | 2 | -0/+26 | |
| * | | | Bump version | github-actions[bot] | 2021-07-30 | 1 | -1/+1 | |
| * | | | opt_lut: Allow more than one -dlogic per cell type. | Marcelina Kościelnicka | 2021-07-29 | 3 | -24/+55 | |
| * | | | verilog: save and restore overwritten macro arguments | Zachary Snow | 2021-07-28 | 4 | -4/+54 | |
| * | | | Bump version | github-actions[bot] | 2021-07-29 | 1 | -1/+1 | |
| * | | | verilog: Emit $meminit_v2 cell. | Marcelina Kościelnicka | 2021-07-28 | 5 | -55/+87 | |
| * | | | backends/verilog: Support meminit with mask. | Marcelina Kościelnicka | 2021-07-28 | 1 | -3/+18 | |
| * | | | memory: Introduce $meminit_v2 cell, with EN input. | Marcelina Kościelnicka | 2021-07-28 | 10 | -13/+86 | |
| * | | | Bump version | github-actions[bot] | 2021-07-28 | 1 | -1/+1 | |
| * | | | proc: Run opt_expr at the end | Marcelina Kościelnicka | 2021-07-27 | 1 | -0/+11 | |
| * | | | opt_expr: Propagate constants to port connections. | Marcelina Kościelnicka | 2021-07-27 | 3 | -3/+37 | |
| * | | | Bump version | github-actions[bot] | 2021-07-27 | 1 | -1/+1 | |
| * | | | Add version bump workflow | Miodrag Milanovic | 2021-07-26 | 1 | -0/+31 | |
| * | | | Update to latest verific | Miodrag Milanovic | 2021-07-21 | 1 | -3/+3 | |
| * | | | Use new read_id_num helper function elsewhere in hierarchy.cc | Rupert Swarbrick | 2021-07-20 | 1 | -5/+6 | |
| * | | | Extract connection checking logic from expand_module in hierarchy.cc | Rupert Swarbrick | 2021-07-20 | 1 | -23/+64 | |
| * | | | Merge pull request #2885 from whitequark/cxxrtl-fix-2883 | whitequark | 2021-07-20 | 1 | -2/+8 | |
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| | * | | | cxxrtl: treat wires with multiple defs as not inlinable. | whitequark | 2021-07-20 | 1 | -2/+8 | |
| * | | | | Merge pull request #2884 from whitequark/cxxrtl-fix-2882 | whitequark | 2021-07-20 | 1 | -10/+12 | |
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| | * | | | cxxrtl: treat assignable internal wires used only for debug as locals. | whitequark | 2021-07-20 | 1 | -10/+12 | |
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| * | | | Merge pull request #2881 from whitequark/cxxrtl-sideways-colon | whitequark | 2021-07-20 | 1 | -1/+14 | |
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| | * | | | cxxrtl: escape colon in variable names in VCD writer. | whitequark | 2021-07-19 | 1 | -1/+14 | |
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| * | | | Merge pull request #2880 from whitequark/cxxrtl-fix-2877 | whitequark | 2021-07-18 | 1 | -0/+16 | |
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| | * | | | cxxrtl: add debug_item::{get,set}. | whitequark | 2021-07-18 | 1 | -0/+16 | |
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| * | | | Merge pull request #2879 from whitequark/cxxrtl-fix-2739-again | whitequark | 2021-07-17 | 1 | -0/+6 | |
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| | * | | | cxxrtl: treat internal wires used only for debug as constants. | whitequark | 2021-07-17 | 1 | -0/+6 | |
| * | | | | Add support for parsing the SystemVerilog 'bind' construct | Rupert Swarbrick | 2021-07-16 | 19 | -4/+247 | |
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| * | | | Merge pull request #2874 from whitequark/cxxrtl-fix-2589 | whitequark | 2021-07-16 | 1 | -9/+6 | |
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| | * | | | cxxrtl: run hierarchy pass regardless of (*top*) attribute presence. | whitequark | 2021-07-16 | 1 | -9/+6 | |
| * | | | | Merge pull request #2873 from whitequark/cxxrtl-fix-2500 | whitequark | 2021-07-16 | 1 | -3/+3 | |
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| | * | | | | cxxrtl: emit debug items for unused public wires. | whitequark | 2021-07-16 | 1 | -3/+3 | |
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| * | | | | Merge pull request #2872 from whitequark/cxxrtl-fix-2521 | whitequark | 2021-07-16 | 1 | -2/+2 | |
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