| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | | * | | | | | Remove '-ignore_unknown_cells' option from 'sat' | Eddie Hung | 2020-04-20 | 1 | -6/+6 | |
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| | | * | | | | | Simplify test case script | Eddie Hung | 2020-04-20 | 1 | -30/+17 | |
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| | | * | | | | | Remove ununsed files | Eddie Hung | 2020-04-20 | 5 | -83/+0 | |
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| | | * | | | | | Modifications of tests as per Eddie's request | diego | 2020-04-20 | 15 | -78/+1237 | |
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| | | * | | | | | Wrong fixed value | diego | 2020-04-17 | 1 | -1/+1 | |
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| | | * | | | | | Adding tests for dynamic part select optimisation | diego | 2020-04-16 | 7 | -0/+161 | |
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| | * | | | | | Make mask-and-shift the default for bitselwrite | Claire Wolf | 2020-04-16 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com> | |||||
| | * | | | | | Add LookaheadRewriter for proper bitselwrite support | Claire Wolf | 2020-04-16 | 4 | -4/+144 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com> | |||||
| | * | | | | | Improved rewrite code for writing to bit slice (disabled for now) | Claire Wolf | 2020-04-15 | 1 | -12/+64 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the new rewrite rule. But it's still missing a check that makes sure the new rewrite rule is actually a valid substitute in the always block being processed. Therefore the new rewrite rule is just disabled for now. Signed-off-by: Claire Wolf <claire@symbioticeda.com> | |||||
| * | | | | | | Merge pull request #1961 from whitequark/paramod-original-name | whitequark | 2020-04-21 | 3 | -11/+7 | |
| |\ \ \ \ \ \ | | | | | | | | | | | | | | | ast, rpc: record original name of $paramod\* as \hdlname attribute | |||||
| | * | | | | | | ast, rpc: record original name of $paramod\* as \hdlname attribute. | whitequark | 2020-04-18 | 3 | -11/+7 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The $paramod name mangling is not invertible (the \ character, which separates the module name from the parameters, is valid in the module name itself), which does not stop people from trying to invert it. This commit makes it easy to invert the name mangling by storing the original name explicitly, and fixes the firrtl backend to use the newly introduced attribute. | |||||
| * | | | | | | | tests: remove write_ilang | Eddie Hung | 2020-04-20 | 2 | -3/+0 | |
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| * | | | | | | | Merge pull request #1972 from YosysHQ/eddie/bug1970 | Eddie Hung | 2020-04-20 | 2 | -16/+52 | |
| |\ \ \ \ \ \ \ | |_|_|/ / / / |/| | | | | | | abc9_ops: -prep_lut to be more robust | |||||
| | * | | | | | | abc9: -prep_lut to be more robust | Eddie Hung | 2020-04-20 | 1 | -16/+33 | |
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| | * | | | | | | abc9: add testcase reduced from #1970 | Eddie Hung | 2020-04-20 | 1 | -0/+19 | |
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| * | | | | | | Merge pull request #1964 from YosysHQ/claire/sformatf | Claire Wolf | 2020-04-20 | 1 | -8/+38 | |
| |\ \ \ \ \ \ | |_|_|_|_|/ |/| | | | | | Extend support for format strings in Verilog front-end | |||||
| | * | | | | | Extend support for format strings in Verilog front-end | Claire Wolf | 2020-04-18 | 1 | -8/+38 | |
| | | |_|/ / | |/| | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com> | |||||
| * | | | | | Merge pull request #1967 from whitequark/cxxrtl-blackbox-attributes | whitequark | 2020-04-19 | 2 | -49/+57 | |
| |\ \ \ \ \ | |/ / / / |/| | | | | cxxrtl: provide attributes to black box factories, too | |||||
| | * | | | | cxxrtl: provide attributes to black box factories, too. | whitequark | 2020-04-19 | 2 | -49/+57 | |
| |/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Both parameters and attributes are necessary because the parameters have to be the same between every instantiation of the cell, but attributes may well vary. For example, for an UART PHY, the type of the PHY (tty, pty, socket) would be a parameter, but configuration of the implementation specified by the type (socket address) would be an attribute. | |||||
| * | | | | Merge pull request #1963 from whitequark/cxxrtl-blackboxes | whitequark | 2020-04-18 | 2 | -198/+637 | |
| |\ \ \ \ | | | | | | | | | | | cxxrtl: add support for simple and templated C++ black boxes | |||||
| | * | | | | cxxrtl: add templated black box support. | whitequark | 2020-04-18 | 1 | -16/+193 | |
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| | * | | | | cxxrtl: make eval() and commit() inline in blackboxes. | whitequark | 2020-04-18 | 1 | -82/+103 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | This change is a preparation for template blackboxes. It has no effect on current generated code. | |||||
| | * | | | | cxxrtl: add simple black box support. | whitequark | 2020-04-18 | 2 | -70/+311 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds support for replacing RTLIL modules with CXXRTL black boxes. Black box port widths may not depend on the parameters with which it is instantiated (yet); the parameters may only be used to change the behavior of the black box. | |||||
| | * | | | | cxxrtl: use ID::X instead of ID(X). NFC. | whitequark | 2020-04-18 | 1 | -107/+107 | |
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| * | | | | Merge pull request #1955 from whitequark/cxxrtl-sync_always | whitequark | 2020-04-17 | 1 | -3/+13 | |
| |\ \ \ \ | | | | | | | | | | | cxxrtl: correctly handle `sync always` rules | |||||
| | * | | | | cxxrtl: correctly handle `sync always` rules. | whitequark | 2020-04-17 | 1 | -3/+13 | |
| | |/ / / | | | | | | | | | | | | | Fixes #1948. | |||||
| * | | | | Merge pull request #1952 from boqwxp/add_edge_location | whitequark | 2020-04-17 | 1 | -0/+3 | |
| |\ \ \ \ | |/ / / |/| | | | Verilog frontend: add source location in more parser rules | |||||
| | * | | | Set Verilog source location for explicit blocks (`begin` ... `end`). | Alberto Gonzalez | 2020-04-17 | 1 | -0/+1 | |
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| | * | | | Add Verilog source location information to `AST_POSEDGE` and `AST_NEGEDGE` ↵ | Alberto Gonzalez | 2020-04-17 | 1 | -0/+2 | |
| | | | | | | | | | | | | | | | | | nodes. | |||||
| * | | | | Merge pull request #1954 from YosysHQ/dave/fix-stdout-conflict | whitequark | 2020-04-17 | 1 | -3/+3 | |
| |\ \ \ \ | | | | | | | | | | | qbfsat: Fix illegal use of 'stdout' identifier | |||||
| | * | | | | qbfsat: Fix illegal use of 'stdout' identifier | David Shah | 2020-04-17 | 1 | -3/+3 | |
| | |/ / / | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | | | Merge pull request #1951 from whitequark/rtlil-string_attribute | whitequark | 2020-04-17 | 2 | -19/+33 | |
| |\ \ \ \ | |/ / / |/| | | | rtlil: add AttrObject::{get,set}_string_attribute, AttrObject::has_attribute | |||||
| | * | | | rtlil: add AttrObject::has_attribute. | whitequark | 2020-04-16 | 2 | -0/+7 | |
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| | * | | | rtlil: add AttrObject::{get,set}_string_attribute. | whitequark | 2020-04-16 | 2 | -19/+26 | |
| | | | | | | | | | | | | | | | | | And make {get,set}_src_attribute use those functions. | |||||
| * | | | | Merge pull request #1898 from boqwxp/locations | whitequark | 2020-04-17 | 1 | -0/+3 | |
| |\ \ \ \ | | | | | | | | | | | Verilog frontend: add location information to parsed constants | |||||
| | * | | | | Add location information to `AST_CONSTANT` nodes. | Alberto Gonzalez | 2020-04-16 | 1 | -0/+3 | |
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| * | | | | Merge pull request #1864 from boqwxp/cleanup_techmap_abc | whitequark | 2020-04-17 | 1 | -99/+80 | |
| |\ \ \ \ | | | | | | | | | | | Clean up pseudo-private member usage and simplify `passes/techmap/abc.cc` | |||||
| | * | | | | Simplify `passes/techmap/abc.cc` and remove superfluous `RTLIL::SigSpec` ↵ | Alberto Gonzalez | 2020-04-14 | 1 | -132/+49 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | constructions. Co-Authored-By: Eddie Hung <eddie@fpgeh.com> | |||||
| | * | | | | Clean up pseudo-private member usage and simplify `passes/techmap/abc.cc`. | Alberto Gonzalez | 2020-04-05 | 1 | -99/+163 | |
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| * | | | | | Merge pull request #1888 from boqwxp/cleanup_scatter | whitequark | 2020-04-17 | 1 | -17/+11 | |
| |\ \ \ \ \ | | | | | | | | | | | | | Clean up `passes/cmds/scatter.cc`. | |||||
| | * | | | | | Replace `std::map` with `dict`. | Alberto Gonzalez | 2020-04-16 | 1 | -2/+2 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com> | |||||
| | * | | | | | Replace pseudo-private member access to `connections_` in ↵ | Alberto Gonzalez | 2020-04-16 | 1 | -13/+10 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | `passes/cmds/scatter.cc`. Co-Authored-By: N. Engelhardt <nak@symbioticeda.com> | |||||
| | * | | | | | Clean up `passes/cmds/scatter.cc`. | Alberto Gonzalez | 2020-04-16 | 1 | -10/+7 | |
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| * | | | | | Merge pull request #1882 from boqwxp/cleanup_rename | whitequark | 2020-04-17 | 1 | -119/+103 | |
| |\ \ \ \ \ | | | | | | | | | | | | | Clean up pseudo-private member usage in `passes/cmds/rename.cc`. | |||||
| | * | | | | | Use `dict` instead of `std::map`. | Alberto Gonzalez | 2020-04-16 | 1 | -9/+9 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com> | |||||
| | * | | | | | Revert to `stringf()` rather than stringstreams. | Alberto Gonzalez | 2020-04-16 | 1 | -12/+8 | |
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| | * | | | | | Clean up pseudo-private member usage in `passes/cmds/rename.cc`. | Alberto Gonzalez | 2020-04-16 | 1 | -119/+107 | |
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| * | | | | | Merge pull request #1929 from YosysHQ/eddie/select_unset | whitequark | 2020-04-16 | 4 | -3/+43 | |
| |\ \ \ \ \ | |_|_|/ / |/| | | | | select: add select -unset option | |||||
| | * | | | | tests: add select -unset tests | Eddie Hung | 2020-04-16 | 2 | -0/+20 | |
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| | * | | | | select: add select -unset option | Eddie Hung | 2020-04-16 | 2 | -3/+23 | |
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