diff options
author | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-04-09 05:34:28 +0000 |
---|---|---|
committer | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-04-16 18:49:55 +0000 |
commit | 0787af947f92d9d1040623b5d2e8c737c0aee0a9 (patch) | |
tree | ebb0e1ef635a2897185247ca6af7cd3c0672a481 | |
parent | 8d3f6d0d792a1cd688ce4d9c05bef8ec601f9334 (diff) | |
download | yosys-0787af947f92d9d1040623b5d2e8c737c0aee0a9.tar.gz yosys-0787af947f92d9d1040623b5d2e8c737c0aee0a9.tar.bz2 yosys-0787af947f92d9d1040623b5d2e8c737c0aee0a9.zip |
Clean up `passes/cmds/scatter.cc`.
-rw-r--r-- | passes/cmds/scatter.cc | 17 |
1 files changed, 7 insertions, 10 deletions
diff --git a/passes/cmds/scatter.cc b/passes/cmds/scatter.cc index 7123ba9fb..8c95e4289 100644 --- a/passes/cmds/scatter.cc +++ b/passes/cmds/scatter.cc @@ -46,22 +46,19 @@ struct ScatterPass : public Pass { CellTypes ct(design); extra_args(args, 1, design); - for (auto &mod_it : design->modules_) + for (auto module : design->selected_modules()) { - if (!design->selected(mod_it.second)) - continue; - - for (auto &c : mod_it.second->cells_) - for (auto &p : c.second->connections_) + for (auto cell : module->cells()) + for (auto &p : cell->connections_) { - RTLIL::Wire *wire = mod_it.second->addWire(NEW_ID, p.second.size()); + RTLIL::Wire *wire = module->addWire(NEW_ID, p.second.size()); - if (ct.cell_output(c.second->type, p.first)) { + if (ct.cell_output(cell->type, p.first)) { RTLIL::SigSig sigsig(p.second, wire); - mod_it.second->connect(sigsig); + module->connect(sigsig); } else { RTLIL::SigSig sigsig(wire, p.second); - mod_it.second->connect(sigsig); + module->connect(sigsig); } p.second = wire; |