diff options
| author | whitequark <whitequark@whitequark.org> | 2020-04-17 18:57:00 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-04-17 18:57:00 +0000 |
| commit | 67fbc00a1824aafb2af2e7c4b7a9590c7bc718fa (patch) | |
| tree | e8af097accd48a51738334df569c846a879005ff | |
| parent | 115fc261e60ebcd0456e26aac452942137db1ca9 (diff) | |
| parent | 00d74f0b9ceecc7b60f50fddb3b6ab0c47701923 (diff) | |
| download | yosys-67fbc00a1824aafb2af2e7c4b7a9590c7bc718fa.tar.gz yosys-67fbc00a1824aafb2af2e7c4b7a9590c7bc718fa.tar.bz2 yosys-67fbc00a1824aafb2af2e7c4b7a9590c7bc718fa.zip | |
Merge pull request #1952 from boqwxp/add_edge_location
Verilog frontend: add source location in more parser rules
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 7447ab8d5..4a5aba79e 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1924,11 +1924,13 @@ always_events: always_event: TOK_POSEDGE expr { AstNode *node = new AstNode(AST_POSEDGE); + SET_AST_NODE_LOC(node, @1, @1); ast_stack.back()->children.push_back(node); node->children.push_back($2); } | TOK_NEGEDGE expr { AstNode *node = new AstNode(AST_NEGEDGE); + SET_AST_NODE_LOC(node, @1, @1); ast_stack.back()->children.push_back(node); node->children.push_back($2); } | @@ -2244,6 +2246,7 @@ behavioral_stmt: exitTypeScope(); if ($4 != NULL && $8 != NULL && *$4 != *$8) frontend_verilog_yyerror("Begin label (%s) and end label (%s) don't match.", $4->c_str()+1, $8->c_str()+1); + SET_AST_NODE_LOC(ast_stack.back(), @2, @8); delete $4; delete $8; ast_stack.pop_back(); |