| Commit message (Expand) | Author | Age | Files | Lines | ||
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| | | * | | | | | | | | Add defvalue test, minor autotest fixes for .sv files | Clifford Wolf | 2019-06-19 | 2 | -14/+37 | |
| | | * | | | | | | | | Use input default values in hierarchy pass | Clifford Wolf | 2019-06-19 | 1 | -0/+38 | |
| | | * | | | | | | | | Add defaultvalue attribute | Clifford Wolf | 2019-06-19 | 2 | -0/+15 | |
| | | * | | | | | | | | Fix handling of "logic" variables with initial value | Clifford Wolf | 2019-06-19 | 1 | -2/+2 | |
| | * | | | | | | | | | Make tests/aiger less chatty | Clifford Wolf | 2019-06-19 | 1 | -4/+6 | |
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| | * | | | | | | | | Merge pull request #1100 from bwidawsk/home | Clifford Wolf | 2019-06-19 | 5 | -0/+8 | |
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| | | * | | | | | | | | Support filename rewrite in backends | Ben Widawsky | 2019-06-18 | 4 | -0/+4 | |
| | | * | | | | | | | | Support ~ for home directory | Ben Widawsky | 2019-06-18 | 1 | -0/+4 | |
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| | * | | | | | | | | Merge pull request #1104 from whitequark/case-semantics | Clifford Wolf | 2019-06-19 | 2 | -1/+40 | |
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| | | * | | | | | | | Explain exact semantics of switch and case rules in the manual. | whitequark | 2019-06-19 | 1 | -0/+12 | |
| | | * | | | | | | | In RTLIL::Module::check(), check process invariants. | whitequark | 2019-06-19 | 1 | -1/+28 | |
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| | * | | | | | | | Merge pull request #1086 from udif/pr_elab_sys_tasks2 | Clifford Wolf | 2019-06-18 | 2 | -3/+13 | |
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| | | * | | | | | | Fixed brojen $error()/$info/$warning() on non-generate blocks | Udi Finkelstein | 2019-06-11 | 2 | -3/+13 | |
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| | * | | | | | | Add timescale and generated-by header to yosys-smtbmc MkVcd | Clifford Wolf | 2019-06-16 | 1 | -0/+2 | |
| * | | | | | | | Fix issue with part of PI being 1'bx | Eddie Hung | 2019-06-20 | 2 | -4/+11 | |
| * | | | | | | | Call opt_expr -mux_undef to get rid of 1'bx in muxes prior to abc | Eddie Hung | 2019-06-20 | 1 | -0/+1 | |
| * | | | | | | | Handle COs driven by 1'bx | Eddie Hung | 2019-06-20 | 1 | -3/+9 | |
| * | | | | | | | Do not call "setundef -zero" in abc9 | Eddie Hung | 2019-06-20 | 1 | -5/+2 | |
| * | | | | | | | write_xaiger to skip POs driven by 1'bx | Eddie Hung | 2019-06-20 | 1 | -3/+7 | |
| * | | | | | | | Really permute Xilinx LUT mappings as default LUT6.I5:A6 | Eddie Hung | 2019-06-18 | 1 | -16/+16 | |
| * | | | | | | | Revert "Fix (do not) permute LUT inputs, but permute mux selects" | Eddie Hung | 2019-06-18 | 1 | -33/+31 | |
| * | | | | | | | Clean up | Eddie Hung | 2019-06-18 | 1 | -6/+4 | |
| * | | | | | | | Fix (do not) permute LUT inputs, but permute mux selects | Eddie Hung | 2019-06-18 | 1 | -31/+33 | |
| * | | | | | | | Fix copy-pasta issue | Eddie Hung | 2019-06-17 | 1 | -9/+8 | |
| * | | | | | | | Permute INIT for +/xilinx/lut_map.v | Eddie Hung | 2019-06-17 | 1 | -32/+58 | |
| * | | | | | | | Simplify comment | Eddie Hung | 2019-06-17 | 1 | -1/+1 | |
| * | | | | | | | Update LUT7/8 delays to take account for [ABC]OUTMUX delay | Eddie Hung | 2019-06-17 | 1 | -5/+5 | |
| * | | | | | | | &scorr before &sweep, remove &retime as recommended | Eddie Hung | 2019-06-17 | 1 | -1/+1 | |
| * | | | | | | | Copy not move parameters/attributes | Eddie Hung | 2019-06-17 | 1 | -3/+4 | |
| * | | | | | | | Fix leak removing cells during ABC integration; also preserve attr | Eddie Hung | 2019-06-17 | 3 | -27/+37 | |
| * | | | | | | | Try -W 300 | Eddie Hung | 2019-06-17 | 1 | -1/+2 | |
| * | | | | | | | Re-enable &dc2 | Eddie Hung | 2019-06-17 | 1 | -1/+1 | |
| * | | | | | | | Cleanup | Eddie Hung | 2019-06-16 | 3 | -299/+33 | |
| * | | | | | | | Fix upper XC7 LUT[78] delays to use I[01] -> O delay not S -> O | Eddie Hung | 2019-06-15 | 1 | -2/+2 | |
| * | | | | | | | Leave breadcrumb behind | Eddie Hung | 2019-06-14 | 1 | -0/+2 | |
| * | | | | | | | Remove redundant condition | Eddie Hung | 2019-06-14 | 1 | -1/+1 | |
| * | | | | | | | Revert "Cleanup/optimise toposort in write_xaiger" | Eddie Hung | 2019-06-14 | 1 | -44/+40 | |
| * | | | | | | | Update comment | Eddie Hung | 2019-06-14 | 1 | -1/+2 | |
| * | | | | | | | Check that whiteboxes are synthesisable | Eddie Hung | 2019-06-14 | 1 | -4/+8 | |
| * | | | | | | | Get rid of compiler warnings | Eddie Hung | 2019-06-14 | 2 | -7/+7 | |
| * | | | | | | | As per @daveshah1 remove async DFF timing from xilinx | Eddie Hung | 2019-06-14 | 1 | -2/+2 | |
| * | | | | | | | Cover __APPLE__ too for little to big endian | Eddie Hung | 2019-06-14 | 2 | -8/+16 | |
| * | | | | | | | Update abc9 -D doc | Eddie Hung | 2019-06-14 | 1 | -1/+2 | |
| * | | | | | | | Enable "abc9 -D <num>" for timing-driven synthesis | Eddie Hung | 2019-06-14 | 1 | -9/+9 | |
| * | | | | | | | Further cleanup based on @daveshah1 | Eddie Hung | 2019-06-14 | 4 | -47/+47 | |
| * | | | | | | | Resolve comments from @daveshah1 | Eddie Hung | 2019-06-14 | 3 | -17/+11 | |
| * | | | | | | | Add XC7_WIRE_DELAY macro to synth_xilinx.cc | Eddie Hung | 2019-06-14 | 1 | -1/+3 | |
| * | | | | | | | Update delays based on SymbiFlow/prjxray-db | Eddie Hung | 2019-06-14 | 1 | -12/+13 | |
| * | | | | | | | Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut} | Eddie Hung | 2019-06-14 | 4 | -3/+3 | |
| * | | | | | | | Comment out dist RAM boxing on ECP5 for now | Eddie Hung | 2019-06-14 | 1 | -1/+1 | |
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index : iCE40/yosys | |
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