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* Add more options and time handlingMiodrag Milanovic2022-01-283-2/+106
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* update versionMiodrag Milanovic2022-01-261-1/+1
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* Display values of outputsMiodrag Milanovic2022-01-261-12/+10
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* Fix tabs/spacesMiodrag Milanovic2022-01-261-31/+31
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* Check if stimulatedMiodrag Milanovic2022-01-261-0/+14
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* Read fst and use data to set inputsMiodrag Milanovic2022-01-261-10/+92
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* Add fstdata helper classMiodrag Milanovic2022-01-263-1/+348
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* Cleanup of config to support platformsMiodrag Milanovic2022-01-261-20/+13
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* Add ability to write to FST fileMiodrag Milanovic2022-01-261-11/+109
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* Add FST libraryMiodrag Milanovic2022-01-2510-0/+9857
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* Bump versiongithub-actions[bot]2022-01-201-1/+1
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* nexus: Fix BB sim modelgatecat2022-01-191-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Removed dbits 8 since 9 will always be pickedMiodrag Milanovic2022-01-191-2/+0
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* Merge pull request #3120 from Icenowy/anlogic-bramMiodrag Milanović2022-01-198-2/+283
|\ | | | | anlogic: support BRAM mapping
| * anlogic: support BRAM mappingIcenowy Zheng2021-12-178-2/+283
| | | | | | | | | | | | | | | | | | | | | | Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being true dual port (or 18bit*512 when simple dual port), the other is 16bit*2K. Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and 32Kbit BRAM with 8bit width are not support yet. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* | Bump versiongithub-actions[bot]2022-01-181-1/+1
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* | Merge pull request #3162 from YosysHQ/mmicko/windows_guidelinesMiodrag Milanović2022-01-171-0/+23
|\ \ | | | | | | Add info about VS build
| * | Update guidelines/WindowsMiodrag Milanović2022-01-171-1/+1
| | | | | | | | | Co-authored-by: N. Engelhardt <nakengelhardt@gmail.com>
| * | Add info about VS buildMiodrag Milanović2022-01-171-0/+23
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* | | Merge pull request #3145 from nakengelhardt/advertise_suite_in_readmeN. Engelhardt2022-01-171-6/+17
|\ \ \ | |/ / |/| | mention tabby+oss cad suite in readme
| * | mention distributions' package managerN. Engelhardt2022-01-171-0/+1
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| * | mention tabby+oss cad suite in readmeN. Engelhardt2022-01-041-6/+16
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* | | Bump versiongithub-actions[bot]2022-01-121-1/+1
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* | | Forgot oneMiodrag Milanovic2022-01-111-1/+1
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* | | Change url to httpsMiodrag Milanovic2022-01-112-2/+2
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* | | Next dev cycleMiodrag Milanovic2022-01-112-2/+5
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* | | Release version 0.13Miodrag Milanovic2022-01-112-3/+3
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* | | Update CHANGELOGMiodrag Milanovic2022-01-111-6/+19
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* | | Bump versiongithub-actions[bot]2022-01-091-1/+1
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* | | sv: auto add nosync to certain always_comb local varsZachary Snow2022-01-0710-0/+265
| | | | | | | | | | | | | | | If a local variable is always assigned before it is used, then adding nosync prevents latches from being needlessly generated.
* | | sv: fix size cast internal expression extensionZachary Snow2022-01-074-2/+156
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* | | Bump versiongithub-actions[bot]2022-01-051-1/+1
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* | | logger: fix unmatched expected warnings and errorsZachary Snow2022-01-042-11/+53
| | | | | | | | | | | | | | | | | | | | | | | | - Prevent unmatched expected error patterns from self-matching - Prevent infinite recursion on unmatched expected warnings - Always print the error message for unmatched error patterns - Add test coverage for all unmatched message types - Add test coverage for excess matched logs and warnings
* | | opt_dff: fix sequence point copy paste bugAustin Seipp2022-01-041-1/+1
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Newer GCCs emit the following warning for opt_dff: passes/opt/opt_dff.cc:560:17: warning: operation on ‘ff.Yosys::FfData::has_clk’ may be undefined [-Wsequence-point] 560 | ff.has_clk = ff.has_ce = ff.has_clk = false; | ~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Which is correct: the order of whether the read or write of has_clk occurs first is undefined since there is no sequence point between them. This is almost certainly just a typo/copy paste error and objectively wrong, so just fix it. Signed-off-by: Austin Seipp <aseipp@pobox.com>
* | manual: Fix cell-stmt ordergatecat2022-01-031-1/+1
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Bump versiongithub-actions[bot]2022-01-041-1/+1
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* | fix iverilog compatibility for new case expr testsZachary Snow2022-01-032-2/+2
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* | fixup verilog doubleslash testZachary Snow2022-01-032-0/+3
| | | | | | | | | | - add generated doubleslash.v to .gitignore - ensure backend verilog can be read again
* | sv: fix size cast clipping expression widthZachary Snow2022-01-033-1/+11
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* | Update manualMiodrag Milanovic2022-01-031-1/+21
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* | Bump versiongithub-actions[bot]2021-12-261-1/+1
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* | Merge pull request #3127 from whitequark/cxxrtl-no-reset-elidedCatherine2021-12-251-0/+2
|\ \ | | | | | | cxxrtl: don't reset elided wires with \init attribute
| * | cxxrtl: don't reset elided wires with \init attribute.Catherine2021-12-251-0/+2
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* | | Bump versiongithub-actions[bot]2021-12-221-1/+1
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* | | intel_alm: disable 256x40 M10K modeLofty2021-12-221-9/+3
| | | | | | | | | | | | | | | This BRAM mode uses both address ports, making it effectively single-port. Since memory_bram can't presently map to single-port memories, remove it.
* | | Bump versiongithub-actions[bot]2021-12-211-1/+1
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* | | memory_share: Fix SAT-based sharing for wide ports.Marcelina Kościelnicka2021-12-202-1/+37
| | | | | | | | | | | | Fixes #3117.
* | | Bump versiongithub-actions[bot]2021-12-191-1/+1
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* | | fix width detection of array querying function in case and case item expressionsZachary Snow2021-12-175-2/+50
| |/ |/| | | | | | | I also removed the unnecessary shadowing of `width_hint` and `sign_hint` in the corresponding case in `simplify()`.
* | Bump versiongithub-actions[bot]2021-12-171-1/+1
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