diff options
| author | Zachary Snow <zach@zachjs.com> | 2021-12-30 00:01:30 -0700 |
|---|---|---|
| committer | Zachary Snow <zachary.j.snow@gmail.com> | 2022-01-03 08:17:35 -0700 |
| commit | 8c509a5659d540dc41f6cc19ee6989fc249f519d (patch) | |
| tree | 95269bdb728345b781ed31c081bd35ed00462cec | |
| parent | cb17eeaf5008a87384b3888dc34993928daba918 (diff) | |
| download | yosys-8c509a5659d540dc41f6cc19ee6989fc249f519d.tar.gz yosys-8c509a5659d540dc41f6cc19ee6989fc249f519d.tar.bz2 yosys-8c509a5659d540dc41f6cc19ee6989fc249f519d.zip | |
sv: fix size cast clipping expression width
| -rw-r--r-- | CHANGELOG | 2 | ||||
| -rw-r--r-- | frontends/ast/genrtlil.cc | 3 | ||||
| -rw-r--r-- | tests/simple/lesser_size_cast.sv | 7 |
3 files changed, 11 insertions, 1 deletions
@@ -16,6 +16,8 @@ Yosys 0.11 .. Yosys 0.12 - Support parameters using struct as a wiretype - Fixed regression preventing the use array querying functions in case expressions and case item expressions + - Fixed static size casts inadvertently limiting the result width of binary + operations * New commands and options - Added "-genlib" option to "abc" pass diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 1fe74bb72..2788a850f 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -932,7 +932,8 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun if (children.at(0)->type != AST_CONSTANT) log_file_error(filename, location.first_line, "Static cast with non constant expression!\n"); children.at(1)->detectSignWidthWorker(width_hint, sign_hint); - width_hint = children.at(0)->bitsAsConst().as_int(); + this_width = children.at(0)->bitsAsConst().as_int(); + width_hint = max(width_hint, this_width); if (width_hint <= 0) log_file_error(filename, location.first_line, "Static cast with zero or negative size!\n"); break; diff --git a/tests/simple/lesser_size_cast.sv b/tests/simple/lesser_size_cast.sv new file mode 100644 index 000000000..8c0bc9814 --- /dev/null +++ b/tests/simple/lesser_size_cast.sv @@ -0,0 +1,7 @@ +module top ( + input signed [1:0] a, + input signed [2:0] b, + output signed [4:0] c +); + assign c = 2'(a) * b; +endmodule |