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* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-20170-416/+414
* Merge pull request #586 from hzeller/more-sourcepos-loggingClifford Wolf2018-07-204-137/+131
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| * Convert more log_error() to log_file_error() where possible.Henner Zeller2018-07-204-137/+131
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* Merge pull request #585 from hzeller/use-file-warning-errorClifford Wolf2018-07-203-82/+79
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| * Use log_file_warning(), log_file_error() functions.Henner Zeller2018-07-203-82/+79
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* Merge pull request #584 from hzeller/provide-source-location-loggingClifford Wolf2018-07-203-47/+47
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| * Provide source-location logging.Henner Zeller2018-07-193-47/+47
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* Add async2sync passClifford Wolf2018-07-192-0/+148
* Fix handling of eventually properties in verific importerClifford Wolf2018-07-171-2/+4
* Fix verific -vlog-incdir and -vlog-libdir handlingClifford Wolf2018-07-161-2/+13
* Merge pull request #581 from daveshah1/ecp5Clifford Wolf2018-07-1610-3/+1200
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| * ecp5: Fixing miscellaneous sim model issuesDavid Shah2018-07-161-2/+2
| * ecp5: Fixing 'X' issues with LUT simulation modelsDavid Shah2018-07-161-6/+19
| * ecp5: ECP5 synthesis fixesDavid Shah2018-07-163-15/+32
| * ecp5: Adding synchronous set/reset supportDavid Shah2018-07-145-24/+197
| * ecp5: Add DRAM match ruleDavid Shah2018-07-131-0/+4
| * ecp5: Cells and mappings fixesDavid Shah2018-07-132-5/+5
| * ecp5: Fixing arith_mapDavid Shah2018-07-131-4/+5
| * ecp5: Initial arith_map implementationDavid Shah2018-07-133-6/+80
| * ecp5: Adding basic synth_ecp5 based on synth_ice40David Shah2018-07-133-7/+345
| * ecp5: Adding DFF mapsDavid Shah2018-07-132-1/+30
| * ecp5: Adding DRAM mapDavid Shah2018-07-133-1/+76
| * ecp5: Adding basic cells_sim and mapper for LUTs up to LUT7David Shah2018-07-132-0/+473
* | Fix "read -incdir"Clifford Wolf2018-07-161-1/+1
* | Merge branch 'master' of github.com:YosysHQ/yosysClifford Wolf2018-07-161-2/+6
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| * | Merge pull request #580 from daveshah1/ice40_nxClifford Wolf2018-07-131-2/+6
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| | * ice40: Add CIN_CONST and CIN_SET parameters to ICESTORM_LCDavid Shah2018-07-131-2/+6
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* / Add "read -incdir"Clifford Wolf2018-07-161-0/+19
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* Fix verific eventually handlingClifford Wolf2018-06-291-6/+5
* Add verific support for eventually propertiesClifford Wolf2018-06-291-5/+105
* Add "verific -formal" and "read -formal"Clifford Wolf2018-06-291-7/+15
* Add "read -sv -D" supportClifford Wolf2018-06-281-2/+25
* Add "read -undef"Clifford Wolf2018-06-281-0/+32
* Fix handling of signed memoriesClifford Wolf2018-06-281-0/+3
* Add YOSYS_NOVERIFIC env variable for temporarily disabling verificClifford Wolf2018-06-221-22/+40
* Add simplified "read" command, enable extnets in implicit Verific importClifford Wolf2018-06-211-0/+84
* Merge branch 'master' of github.com:YosysHQ/yosysClifford Wolf2018-06-201-1/+1
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| * Merge pull request #572 from q3k/q3k/fix-protobuf-buildClifford Wolf2018-06-201-1/+1
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| | * Fix protobuf buildSergiusz Bazanski2018-06-201-1/+1
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* / Add automatic verific import in hierarchy commandClifford Wolf2018-06-203-1/+75
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* Merge pull request #571 from q3k/q3k/protobuf-backendClifford Wolf2018-06-195-0/+560
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| * Add Protobuf backendSerge Bazanski2018-06-195-0/+560
* | Be slightly less aggressive in "deminout" passClifford Wolf2018-06-191-4/+28
* | Merge pull request #570 from edcote/patch-4Clifford Wolf2018-06-191-4/+4
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| * Include module name for area summary statsEdmond Cote2018-06-181-4/+4
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* Bugfix in liberty parser (as suggested by aiju in #569)Clifford Wolf2018-06-151-1/+1
* Add "synth_ice40 -json"Clifford Wolf2018-06-131-9/+22
* Fix ice40_opt for cases where a port is connected to a signal with width != 1Clifford Wolf2018-06-111-9/+25
* Merge pull request #561 from udif/pr_skip_typoClifford Wolf2018-06-061-1/+1
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| * Fixed typo (sikp -> skip)Udi Finkelstein2018-06-051-1/+1
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