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| | | | | | | * GrammarEddie Hung2019-08-091-1/+1
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| | | | | | | * Separate $alu handlingEddie Hung2019-08-091-7/+50
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| | | | | | | * Add $alu testsEddie Hung2019-08-091-0/+42
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| | | | | | | * opt_expr -fine to trim LSBs of $alu tooEddie Hung2019-08-091-4/+9
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| | | | | | | * Add alumacc versions of opt_expr testsEddie Hung2019-08-091-0/+84
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| | | | | | | * Add new $alu test, remove wreduceEddie Hung2019-08-091-11/+21
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| | | | | | | * Cleanup some moreEddie Hung2019-08-091-12/+0
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| | | | | | | * Simplify opt_expr tests using equiv_optEddie Hung2019-08-091-72/+23
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| * | | | | | Merge pull request #1264 from YosysHQ/eddie/fix_1254Eddie Hung2019-08-081-0/+6
| |\ \ \ \ \ \ | | | | | | | | | | | | | | | | opt_lut to ignore LUT cells, or those that drive bits, with (* keep *)
| | * | | | | | opt_lut to ignore LUT cells, or those that drive bits, with (* keep *)Eddie Hung2019-08-071-0/+6
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| * | | | | | Merge pull request #1266 from YosysHQ/eddie/ice40_full_adderEddie Hung2019-08-0820-180/+180
| |\ \ \ \ \ \ | | |/ / / / / | |/| | | | | Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER
| | * | | | | Remove dump callEddie Hung2019-08-071-1/+0
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| | * | | | | Move tests/various/opt* into tests/opt/Eddie Hung2019-08-075-1/+1
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| | * | | | | Remove ice40_unlut call, simply do equiv_opt on synth_ice40Eddie Hung2019-08-071-3/+1
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| | * | | | | Add testcase from removed opt_ff.{v,ys}Eddie Hung2019-08-071-0/+32
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| | * | | | | Remove tests/opt/opt_ff.{v,ys} as they don't seem to do anything but runEddie Hung2019-08-072-24/+0
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| | * | | | | Allow whitebox modules to be overwrittenEddie Hung2019-08-072-3/+1
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| | * | | | | Update CHANGELOGEddie Hung2019-08-071-0/+2
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| | * | | | | Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPEREddie Hung2019-08-076-10/+128
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| | * | | | | Add testEddie Hung2019-08-071-1/+10
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| | * | | | | Remove ice40_unlutEddie Hung2019-08-072-107/+0
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| | * | | | | Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDEREddie Hung2019-08-073-39/+14
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* | | | | | Check nusers of DSP output, not whole flopEddie Hung2019-08-091-1/+1
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* | | | | | Improve ice40_dsp for non-fully-32-bit addersEddie Hung2019-08-091-3/+8
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* | | | | | Add wreduce to synth_ice40 -dsp as wellEddie Hung2019-08-091-0/+1
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* | | | | | Another filter -> ifEddie Hung2019-08-091-2/+2
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* | | | | | CleanupEddie Hung2019-08-092-18/+18
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* | | | | | Pack partial-product adder DSP48E1 packingEddie Hung2019-08-093-10/+81
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* | | | | | Fix checkEddie Hung2019-08-091-4/+6
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* | | | | | Revert "Fix typo"Eddie Hung2019-08-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This reverts commit e3c39cc450a0317ad7e8234bb866d55465548c9c.
* | | | | | Remove muxY and ffY for nowEddie Hung2019-08-082-35/+33
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* | | | | | Remove signed from ports in +/xilinx/dsp_map.vEddie Hung2019-08-081-1/+1
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* | | | | | Rework ice40_dsp to map to SB_MAC16 earlier, and check before packingEddie Hung2019-08-086-40/+119
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* | | | | | Combine techmap callsEddie Hung2019-08-081-2/+1
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* | | | | | Only pack registers if {A,B,P}REG = 0, do not pack $dffeEddie Hung2019-08-081-3/+6
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* | | | | | Move xilinx_dsp to before alumaccEddie Hung2019-08-081-6/+4
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* | | | | | Disable $dffeEddie Hung2019-08-081-8/+8
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* | | | | | INMODE is 5 bitsEddie Hung2019-08-081-1/+1
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* | | | | | Fix copy-pasta typoEddie Hung2019-08-081-2/+2
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* | | | | | ecp5: Replace '-dsp' with inverse logic '-nodsp' to match synth_xilinxDavid Shah2019-08-081-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | ecp5: Bring up to date with mul2dsp changesDavid Shah2019-08-082-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspDavid Shah2019-08-0852-562/+1165
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| * | | | | | Fix compile errorEddie Hung2019-08-071-2/+2
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| * | | | | | Run "opt_expr -fine" instead of "wreduce" due to #1213Eddie Hung2019-08-071-2/+1
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| * | | | | | Do not SigSpec::extract() beyond boundsEddie Hung2019-08-072-8/+10
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| * | | | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-0749-552/+1134
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| | * | | | | Merge pull request #1248 from YosysHQ/eddie/abc9_speedupEddie Hung2019-08-074-40/+48
| | |\ \ \ \ \ | | | |_|/ / / | | |/| | | | abc9: speedup by using using "clean" more efficiently
| | | * | | | Add commentEddie Hung2019-08-071-2/+3
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| | | * | | | Revert "Add TODO"Eddie Hung2019-08-071-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 6068a6bf0d91e3ab9a5eaa33894a816f1560f99a.
| | | * | | | Add TODOEddie Hung2019-08-071-0/+2
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