aboutsummaryrefslogtreecommitdiffstats
Commit message (Expand)AuthorAgeFilesLines
...
| * | | | | | | | | | | | | | | | | | | | | | | | | Add doc for "test_autotb -seed" optionEddie Hung2019-07-261-0/+3
| * | | | | | | | | | | | | | | | | | | | | | | | | Pop the CO bit from OEddie Hung2019-07-261-1/+3
| * | | | | | | | | | | | | | | | | | | | | | | | | Allow adders/accumulators with 33 bits using CO outputEddie Hung2019-07-261-3/+8
| * | | | | | | | | | | | | | | | | | | | | | | | | Add copyright header, comment on cascadeEddie Hung2019-07-241-4/+34
| * | | | | | | | | | | | | | | | | | | | | | | | | Eliminate warnings by sizing O correctlyEddie Hung2019-07-231-1/+5
| * | | | | | | | | | | | | | | | | | | | | | | | | Typo for Y_WIDTHEddie Hung2019-07-231-1/+1
| * | | | | | | | | | | | | | | | | | | | | | | | | Fix muxAB logicEddie Hung2019-07-231-3/+2
| * | | | | | | | | | | | | | | | | | | | | | | | | Remove debug printEddie Hung2019-07-231-1/+1
| * | | | | | | | | | | | | | | | | | | | | | | | | Simplify and fix for MACsEddie Hung2019-07-232-56/+38
| * | | | | | | | | | | | | | | | | | | | | | | | | Fix typoEddie Hung2019-07-231-13/+21
| * | | | | | | | | | | | | | | | | | | | | | | | | Fix spacingEddie Hung2019-07-221-2/+2
| * | | | | | | | | | | | | | | | | | | | | | | | | Remove debugEddie Hung2019-07-221-1/+0
| * | | | | | | | | | | | | | | | | | | | | | | | | Pack hi and lo registers separatelyEddie Hung2019-07-222-39/+70
| * | | | | | | | | | | | | | | | | | | | | | | | | SigSpec::extract() to return as many bits as poss if out of boundsEddie Hung2019-07-221-1/+7
| * | | | | | | | | | | | | | | | | | | | | | | | | Rename according to vendor doc TN1295Eddie Hung2019-07-223-55/+56
| * | | | | | | | | | | | | | | | | | | | | | | | | Pack Y registerEddie Hung2019-07-222-22/+38
| * | | | | | | | | | | | | | | | | | | | | | | | | opt and wreduce necessary for -dspEddie Hung2019-07-221-2/+4
| * | | | | | | | | | | | | | | | | | | | | | | | | Pack adders not just accumulatorsEddie Hung2019-07-222-16/+33
| * | | | | | | | | | | | | | | | | | | | | | | | | Use minimum sized width wiresEddie Hung2019-07-221-7/+13
| * | | | | | | | | | | | | | | | | | | | | | | | | Restore old ffY behaviourEddie Hung2019-07-191-16/+5
| * | | | | | | | | | | | | | | | | | | | | | | | | CleanupEddie Hung2019-07-191-5/+5
| * | | | | | | | | | | | | | | | | | | | | | | | | Indirection via $__soft_mulEddie Hung2019-07-192-9/+10
| * | | | | | | | | | | | | | | | | | | | | | | | | Do not do sign extension in techmap; let packer do itEddie Hung2019-07-191-14/+5
| * | | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/eddie/wreduce_add' into ice40dspEddie Hung2019-07-193-5/+29
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \
| * \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/eddie/wreduce_add' into ice40dspEddie Hung2019-07-192-3/+121
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \
| * | | | | | | | | | | | | | | | | | | | | | | | | | | Do not $mul -> $__mul if A and B are less than maxwidthEddie Hung2019-07-191-1/+3
| * | | | | | | | | | | | | | | | | | | | | | | | | | | Add DSP_MINWIDTH=11 for ice40 since ice40_dsp uses this thresholdEddie Hung2019-07-191-1/+1
| * | | | | | | | | | | | | | | | | | | | | | | | | | | Add a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH,B_WIDTH} <= 1 tooEddie Hung2019-07-191-28/+68
| * | | | | | | | | | | | | | | | | | | | | | | | | | | Fine tune ice40_dsp.pmg, add support for packing subsets of registersEddie Hung2019-07-194-35/+47
| * | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for ice40 signed multipliersEddie Hung2019-07-191-13/+8
| * | | | | | | | | | | | | | | | | | | | | | | | | | | Merge branch 'xc7dsp' into ice40dspEddie Hung2019-07-191-1/+1
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | Fix typo in BEddie Hung2019-07-191-1/+1
| | * | | | | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-07-1829-228/+405
| | |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \
| * | \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ Merge remote-tracking branch 'origin/eddie/signed_ice40_dsp' into ice40dspEddie Hung2019-07-193-7/+239
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use sign_headroom insteadEddie Hung2019-07-191-4/+4
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix SB_MAC sim model -- do not sign extend internal products?Eddie Hung2019-07-181-2/+2
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add paramsEddie Hung2019-07-181-0/+6
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into ice40dspEddie Hung2019-07-181-33/+18
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | |_|/ / / / / / / / / / / / / / / / / / / / / / / / / / / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not define `DSP_SIGNEDONLY macro if no existsEddie Hung2019-07-181-4/+3
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into ice40dspEddie Hung2019-07-1828-195/+387
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ice40_dsp to accept $__MUL16X16 tooEddie Hung2019-07-181-1/+1
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | synth_ice40 to decompose into 16x16Eddie Hung2019-07-181-1/+3
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mul2dsp to create cells that can be interchanged with $mulEddie Hung2019-07-181-1/+7
| | |_|_|/ / / / / / / / / / / / / / / / / / / / / / / / / / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | |
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Check if RHS is empty firstEddie Hung2019-07-181-0/+2
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make consistentEddie Hung2019-07-181-1/+2
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not autoremove ffP aor muxPEddie Hung2019-07-181-2/+0
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Improve pattern matcher to match subsets of $dffe? cellsEddie Hung2019-07-182-12/+22
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Improve A/B reg packingEddie Hung2019-07-182-6/+11
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not autoremove A/B registers since they might have other consumersEddie Hung2019-07-181-2/+0
| * | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix xilinx_dsp index castEddie Hung2019-07-181-2/+2
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-22 03:46:25 +0000