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* proc_memwr: Use the v2 memwr cell.Marcelina Kościelnicka2021-08-113-14/+24
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* Add v2 memory cells.Marcelina Kościelnicka2021-08-1122-206/+631
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* Bump versiongithub-actions[bot]2021-08-111-1/+1
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* kernel/mem: Introduce transparency masks.Marcelina Kościelnicka2021-08-118-118/+408
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* Allow optional comma after last entry in enumMichael Singer2021-08-091-11/+12
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* Bump versiongithub-actions[bot]2021-08-101-1/+1
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* Refactor common parts of SAT-using optimizations into a helper.Marcelina Kościelnicka2021-08-097-153/+224
| | | | | | | | | | | | | This also aligns the functionality: - in all cases, the onehot attribute is used to create appropriate constraints (previously, opt_dff didn't do it at all, and share created one-hot constraints based on $pmux presence alone, which is unsound) - in all cases, shift and mul/div/pow cells are now skipped when importing the SAT problem (previously only memory_share did this) — this avoids creating clauses for hard cells that are unlikely to help with proving the UNSATness needed for optimization
* Bump versiongithub-actions[bot]2021-08-081-1/+1
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* opt_merge: Use FfInitVals.Marcelina Kościelnicka2021-08-083-28/+51
| | | | Partial #2920 fix.
* Bump versiongithub-actions[bot]2021-08-071-1/+1
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* verilog: Support tri/triand/trior wire types.Marcelina Kościelnicka2021-08-061-0/+3
| | | | | | These are, by the standard, just aliases for wire/wand/wor. Fixes #2918.
* Bump versiongithub-actions[bot]2021-08-051-1/+1
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* memory_share: Don't skip ports with EN wired to input for SAT sharing.Marcelina Kościelnicka2021-08-041-3/+1
| | | | Fixes #2912.
* Bump versiongithub-actions[bot]2021-08-041-1/+1
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* memory_bram: Move init data swizzling before other swizzling.Marcelina Kościelnicka2021-08-031-18/+18
| | | | Fixes #2907.
* Bump versiongithub-actions[bot]2021-08-031-1/+1
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* Require latest verificMiodrag Milanovic2021-08-021-1/+1
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* Bump versiongithub-actions[bot]2021-08-021-1/+1
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* backend/verilog: Add alternate mode for transparent read port output.Marcelina Kościelnicka2021-08-011-1/+71
| | | | | | This mode will be used whenever read port cannot be handled in the "extract address register" way, ie. whenever it has enable, reset, init functionality or (in the future) mixed transparency mask.
* memory_bram: Some refactoringMarcelina Kościelnicka2021-08-011-196/+174
| | | | | | This will make more sense when the new transparency masks land. Fixes #2902.
* Bump versiongithub-actions[bot]2021-07-311-1/+1
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* Update version.ymlMiodrag Milanović2021-07-301-2/+5
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* Fixes xc7 BRAM36sMaciej Dudek2021-07-301-4/+6
| | | | | | UG473 from Xilinx states that 15 bit should always be set if RAMB isn't in cascade mode. Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
* proc_rmdead: use explicit pattern set when there are no wildcardsZachary Snow2021-07-294-2/+386
| | | | | | | | If width of a case expression was large, explicit patterns could cause the existing logic to take an extremely long time, or exhaust the maximum size of the underlying set. For cases where all of the patterns are fully defined and there are no constants in the case expression, this change uses a simple set to track which patterns have been seen.
* genrtlil: add width detection for AST_PREFIX nodesZachary Snow2021-07-292-0/+26
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* Bump versiongithub-actions[bot]2021-07-301-1/+1
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* opt_lut: Allow more than one -dlogic per cell type.Marcelina Kościelnicka2021-07-293-24/+55
| | | | Fixes #2061.
* verilog: save and restore overwritten macro argumentsZachary Snow2021-07-284-4/+54
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* Bump versiongithub-actions[bot]2021-07-291-1/+1
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* verilog: Emit $meminit_v2 cell.Marcelina Kościelnicka2021-07-285-55/+87
| | | | Fixes #2447.
* backends/verilog: Support meminit with mask.Marcelina Kościelnicka2021-07-281-3/+18
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* memory: Introduce $meminit_v2 cell, with EN input.Marcelina Kościelnicka2021-07-2810-13/+86
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* Bump versiongithub-actions[bot]2021-07-281-1/+1
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* proc: Run opt_expr at the endMarcelina Kościelnicka2021-07-271-0/+11
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* opt_expr: Propagate constants to port connections.Marcelina Kościelnicka2021-07-273-3/+37
| | | | | | | | This adds one simple piece of functionality to opt_expr: when a cell port is connected to a fully-constant signal (as determined by sigmap), the port is reconnected directly to the constant value. This is just enough optimization to fix the "non-constant $meminit input" problem without requiring a full opt_clean or a separate pass.
* Bump versiongithub-actions[bot]2021-07-271-1/+1
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* Add version bump workflowMiodrag Milanovic2021-07-261-0/+31
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* Update to latest verificMiodrag Milanovic2021-07-211-3/+3
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* Use new read_id_num helper function elsewhere in hierarchy.ccRupert Swarbrick2021-07-201-5/+6
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* Extract connection checking logic from expand_module in hierarchy.ccRupert Swarbrick2021-07-201-23/+64
| | | | | No functional change, but pulls more logic out of the expand_module function.
* Merge pull request #2885 from whitequark/cxxrtl-fix-2883whitequark2021-07-201-2/+8
|\ | | | | cxxrtl: treat wires with multiple defs as not inlinable
| * cxxrtl: treat wires with multiple defs as not inlinable.whitequark2021-07-201-2/+8
| | | | | | | | Fixes #2883.
* | Merge pull request #2884 from whitequark/cxxrtl-fix-2882whitequark2021-07-201-10/+12
|\ \ | |/ |/| cxxrtl: treat assignable internal wires used only for debug as locals
| * cxxrtl: treat assignable internal wires used only for debug as locals.whitequark2021-07-201-10/+12
|/ | | | | | This issue was introduced in commit 4aa65f40 while fixing #2739. Fixes #2882.
* Merge pull request #2881 from whitequark/cxxrtl-sideways-colonwhitequark2021-07-201-1/+14
|\ | | | | cxxrtl: escape colon in variable names in VCD writer
| * cxxrtl: escape colon in variable names in VCD writer.whitequark2021-07-191-1/+14
|/ | | | | | | | | | | | The following VCD file crashes GTKWave's VCD loader: $var wire 1 ! x:1 $end $enddefinitions $end In practice, a colon can be a part of a variable name that is translated from a Verilog function, something like: update$func$.../hdl/hazard3_csr.v:350$2534.$result
* Merge pull request #2880 from whitequark/cxxrtl-fix-2877whitequark2021-07-181-0/+16
|\ | | | | cxxrtl: add debug_item::{get,set}
| * cxxrtl: add debug_item::{get,set}.whitequark2021-07-181-0/+16
|/ | | | Fixes #2877.
* Merge pull request #2879 from whitequark/cxxrtl-fix-2739-againwhitequark2021-07-171-0/+6
|\ | | | | cxxrtl: treat internal wires used only for debug as constants
| * cxxrtl: treat internal wires used only for debug as constants.whitequark2021-07-171-0/+6
| | | | | | | | Fixes #2739 (again).
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