iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Ignore explicit assignments to constants in HDL code	Clifford Wolf	2015-02-08	1	-0/+14
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*	Fixed a bug with autowire bit size	Clifford Wolf	2015-02-08	1	-9/+3
\| \| \| \|	(removed leftover from when we tried to auto-size the wires)
*	fixed typo	Clifford Wolf	2015-02-08	1	-1/+1
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*	Added "yosys-config --build modname.so cppsources.."	Clifford Wolf	2015-02-08	1	-2/+12
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*	Added SigSpec::has_const()	Clifford Wolf	2015-02-08	2	-0/+13
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*	Cleanup in add_share_file make macro	Clifford Wolf	2015-02-08	1	-3/+3
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*	Removed "make mklibyosys"	Clifford Wolf	2015-02-07	1	-14/+0
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*	Improved building of plugins	Clifford Wolf	2015-02-07	2	-3/+36
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*	Added "make uninstall"	Clifford Wolf	2015-02-07	1	-0/+4
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*	Added cell->known(), cell->input(portname), cell->output(portname)	Clifford Wolf	2015-02-07	2	-0/+39
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*	Added "select -read"	Clifford Wolf	2015-02-06	1	-5/+39
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*	Auto-detect TCL version	Clifford Wolf	2015-02-05	2	-2/+2
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*	Added onehot attribute	Clifford Wolf	2015-02-04	3	-0/+19
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*	Fixed opt_clean performance bug	Clifford Wolf	2015-02-04	1	-26/+26
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*	Disabled (unused) Xilinx tristate buffers	Clifford Wolf	2015-02-04	1	-6/+6
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*	Using design->selected_modules() in opt_*	Clifford Wolf	2015-02-03	5	-36/+20
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*	Skip blackbox modules in design->selected_modules()	Clifford Wolf	2015-02-03	1	-3/+5
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*	Added "yosys -L logfile"	Clifford Wolf	2015-02-03	1	-1/+7
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*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2015-02-01	2	-3/+3
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\| *	Merge pull request #48 from rubund/master	Clifford Wolf	2015-02-01	2	-3/+3
\| \|\ \| \| \| \| \| \|	Fixed typos found by lintian
\| \| *	Fixed typos found by lintian	Ruben Undheim	2015-02-01	2	-3/+3
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* \| \|	no support for 6-series xilinx devices	Clifford Wolf	2015-02-01	1	-1/+1
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* /	Improved performance in equiv_simple	Clifford Wolf	2015-02-01	2	-23/+73
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*	Removed old XST-based xilinx examples	Clifford Wolf	2015-02-01	11	-208/+0
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*	Added Xilinx example for Basys3 board	Clifford Wolf	2015-02-01	9	-1/+84
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*	Added EDIF backend support for multi-bit cell ports	Clifford Wolf	2015-02-01	1	-11/+10
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*	Added missing ports and parameters to xilinx brams	Clifford Wolf	2015-02-01	1	-4/+18
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*	Added "make mklibyosys", some minor API changes	Clifford Wolf	2015-02-01	7	-11/+70
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*	Minor README changes	Clifford Wolf	2015-02-01	1	-3/+2
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*	Removed TODO list from README file	Clifford Wolf	2015-02-01	1	-30/+0
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*	Added yosys_banner(), Updated Copyright range	Clifford Wolf	2015-02-01	4	-26/+31
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*	Added <algorithm> include to hashlib.h	Clifford Wolf	2015-02-01	1	-0/+1
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*	Using selections in "ls" command	Clifford Wolf	2015-02-01	1	-34/+30
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*	Shorter "dump" options	Clifford Wolf	2015-01-31	1	-4/+4
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*	Bugfix in opt_const $eq -> buffer code	Clifford Wolf	2015-01-31	1	-4/+4
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*	Log msg change	Clifford Wolf	2015-01-31	1	-1/+1
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*	Fixed equiv_make for partially undriven nets (e.g. after "clean -purge")	Clifford Wolf	2015-01-31	1	-12/+31
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*	Added "equiv_induct -undef"	Clifford Wolf	2015-01-31	2	-6/+51
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*	Added "equiv_simple -undef"	Clifford Wolf	2015-01-31	2	-17/+61
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*	Added "equiv_make -blacklist <file> -encfile <file>"	Clifford Wolf	2015-01-31	4	-5/+189
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*	Synced RTLIL::unescape_id() to log_id() behavior	Clifford Wolf	2015-01-30	1	-3/+9
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*	Added "fsm -encfile"	Clifford Wolf	2015-01-30	3	-14/+50
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*	More log_id() stuff	Clifford Wolf	2015-01-30	1	-3/+7
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*	Some cleanups in log.cc	Clifford Wolf	2015-01-30	1	-14/+16
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*	Improved an error message	Clifford Wolf	2015-01-28	1	-1/+1
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*	Fixed bug in equiv_miter	Clifford Wolf	2015-01-28	1	-6/+6
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*	Added "sat -show-ports"	Clifford Wolf	2015-01-27	1	-2/+7
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*	Bugfix in resource sharing test	Clifford Wolf	2015-01-27	1	-1/+1
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*	Updaed ABC to hg rev 61ad5f908c03	Clifford Wolf	2015-01-27	1	-1/+1
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*	Rethrow with "catch(...) throw;"	Clifford Wolf	2015-01-25	3	-6/+6
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