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* iverilog with simcells.v as wellEddie Hung2019-05-031-1/+2
* Merge pull request #969 from YosysHQ/clifford/pmgenstuffClifford Wolf2019-05-0313-151/+509
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| * Update pmgen documentationClifford Wolf2019-05-031-6/+18
| * Fix typoClifford Wolf2019-05-031-1/+1
| * Add peepopt_muldiv, fixes #930Clifford Wolf2019-04-306-1/+86
| * pmgen progressClifford Wolf2019-04-304-13/+27
| * Run "peepopt" in generic "synth" pass and "synth_ice40"Clifford Wolf2019-04-302-0/+4
| * Some pmgen reorg, rename peepopt.pmg to peepopt_shiftmul.pmgClifford Wolf2019-04-303-4/+6
| * Progress in shiftmul peepopt patternClifford Wolf2019-04-301-3/+51
| * Add "peepopt" skeletonClifford Wolf2019-04-295-1/+112
| * Add pmgen support for multiple patterns in one matcherClifford Wolf2019-04-293-130/+188
| * Support multiple pmg files (right now just concatenated together)Clifford Wolf2019-04-291-6/+30
* | Merge pull request #984 from YosysHQ/eddie/fix_982Clifford Wolf2019-05-031-1/+2
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| * | Revert "synth_xilinx to call dffinit with -noreinit"Eddie Hung2019-05-031-1/+1
| * | If init is 1'bx, do not add to dict as per @cliffordwolfEddie Hung2019-05-031-1/+2
| * | Revert "dffinit -noreinit to silently continue when init value is 1'bx"Eddie Hung2019-05-031-12/+4
| * | synth_xilinx to call dffinit with -noreinitEddie Hung2019-05-021-1/+1
| * | dffinit -noreinit to silently continue when init value is 1'bxEddie Hung2019-05-021-4/+12
* | | Merge pull request #976 from YosysHQ/clifford/fix974Clifford Wolf2019-05-033-0/+25
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| * | | Add splitcmplxassign test case and silence splitcmplxassign warningClifford Wolf2019-05-012-0/+23
| * | | Fix width detection of memory access with bit slice, fixes #974Clifford Wolf2019-05-011-0/+2
* | | | Merge pull request #985 from YosysHQ/clifford/fix981Clifford Wolf2019-05-032-44/+81
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| * | | | Improve opt_expr and opt_clean handling of (partially) undriven and/or unused...Clifford Wolf2019-05-032-44/+81
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* | | | Fix typo in tests/svinterfaces/runone.shClifford Wolf2019-05-031-2/+2
* | | | Merge pull request #979 from jakobwenzel/svinterfacesTestcaseClifford Wolf2019-05-031-2/+2
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| * | | fail svinterfaces testcases on yosys error exitJakob Wenzel2019-05-021-2/+2
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* | | Merge pull request #963 from YosysHQ/eddie/synth_xilinx_fineClifford Wolf2019-05-023-34/+30
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| * | | Back to passing all xc7srl tests!Eddie Hung2019-05-011-5/+4
| * | | Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx_fineEddie Hung2019-05-0122-190/+286
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| * | | | WIPEddie Hung2019-04-281-36/+22
| * | | | Move neg-pol to pos-pol mapping from ff_map to cells_map.vEddie Hung2019-04-282-9/+12
| * | | | Revert synth_xilinx 'fine' label more to how it used to be...Eddie Hung2019-04-261-21/+40
* | | | | Merge pull request #978 from ucb-bar/fmtfirrtlEddie Hung2019-05-011-25/+25
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| * | | | Re-indent firrtl.cc:struct memory - no functional change.Jim Lawson2019-05-011-25/+25
* | | | | Merge branch 'master' of github.com:YosysHQ/yosysEddie Hung2019-05-0121-176/+273
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| * | | | Merge branch 'clifford/fix883'Clifford Wolf2019-05-021-0/+1
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| | * | | | Add missing enable_undef to "sat -tempinduct-def", fixes #883Clifford Wolf2019-05-021-0/+1
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| * | | | Merge pull request #977 from ucb-bar/fixfirrtlmemClifford Wolf2019-05-013-4/+64
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| | * | | | Fix #938 - Crash occurs in case when use write_firrtl commandJim Lawson2019-05-013-4/+64
| * | | | | Fix floating point exception in qwp, fixes #923Clifford Wolf2019-05-011-1/+1
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| * | | | Fix segfault in wreduceClifford Wolf2019-04-301-0/+2
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| * | | Disabled "final loop assignment" featureClifford Wolf2019-04-301-0/+2
| * | | Merge pull request #972 from YosysHQ/clifford/fix968Clifford Wolf2019-04-301-0/+7
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| | * | | Add final loop variable assignment when unrolling for-loops, fixes #968Clifford Wolf2019-04-301-0/+7
| * | | | Merge pull request #966 from YosysHQ/clifford/fix956Clifford Wolf2019-04-303-3/+55
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| | * | | | Add handling of init attributes in "opt_expr -undriven"Clifford Wolf2019-04-302-3/+42
| | * | | | Drive dangling wires with init attr with their init value, fixes #956Clifford Wolf2019-04-291-0/+13
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| * | | | Merge pull request #962 from YosysHQ/eddie/refactor_synth_xilinxClifford Wolf2019-04-302-156/+101
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| | * \ \ \ Merge branch 'master' into eddie/refactor_synth_xilinxClifford Wolf2019-04-309-12/+40
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| * | | | | Merge pull request #973 from christian-krieg/feature/python_bindingsClifford Wolf2019-04-303-4/+4
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