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| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-02 17:41:20 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-02 17:41:20 -0700 |
| commit | 1f62dc9081feb4852b1848d01951f631853edb38 (patch) | |
| tree | 28284627cdf8c692f5aa7c09f629dff25703350a | |
| parent | aa081f83c791b1d666214776aaf744a80ce6a690 (diff) | |
| download | yosys-1f62dc9081feb4852b1848d01951f631853edb38.tar.gz yosys-1f62dc9081feb4852b1848d01951f631853edb38.tar.bz2 yosys-1f62dc9081feb4852b1848d01951f631853edb38.zip | |
synth_xilinx to call dffinit with -noreinit
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 8aa7b508e..fc0e76bad 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -250,7 +250,7 @@ struct SynthXilinxPass : public ScriptPass if (!nosrl || help_mode) run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')"); run("techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v"); - run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " + run("dffinit -noreinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT"); run("clean"); } |