diff options
Diffstat (limited to 'tests/ecp5')
39 files changed, 3200 insertions, 0 deletions
diff --git a/tests/ecp5/.gitignore b/tests/ecp5/.gitignore new file mode 100644 index 000000000..1d329c933 --- /dev/null +++ b/tests/ecp5/.gitignore @@ -0,0 +1,2 @@ +*.log +/run-test.mk diff --git a/tests/ecp5/add_sub.v b/tests/ecp5/add_sub.v new file mode 100644 index 000000000..177c32e30 --- /dev/null +++ b/tests/ecp5/add_sub.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x + y; +assign B = x - y; + +endmodule diff --git a/tests/ecp5/add_sub.ys b/tests/ecp5/add_sub.ys new file mode 100644 index 000000000..03aec6694 --- /dev/null +++ b/tests/ecp5/add_sub.ys @@ -0,0 +1,8 @@ +read_verilog add_sub.v +hierarchy -top top +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 10 t:LUT4 +select -assert-none t:LUT4 %% t:* %D + diff --git a/tests/ecp5/adffs.v b/tests/ecp5/adffs.v new file mode 100644 index 000000000..93c8bf52c --- /dev/null +++ b/tests/ecp5/adffs.v @@ -0,0 +1,91 @@ +module adff + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge clr ) + if ( clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module adffn + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, negedge clr ) + if ( !clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module dffsr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge pre, posedge clr ) + if ( clr ) + q <= 1'b0; + else if ( pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module ndffnsnr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( negedge clk, negedge pre, negedge clr ) + if ( !clr ) + q <= 1'b0; + else if ( !pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module top ( +input clk, +input clr, +input pre, +input a, +output b,b1,b2,b3 +); + +dffsr u_dffsr ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b ) + ); + +ndffnsnr u_ndffnsnr ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b1 ) + ); + +adff u_adff ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b2 ) + ); + +adffn u_adffn ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b3 ) + ); + +endmodule diff --git a/tests/ecp5/adffs.ys b/tests/ecp5/adffs.ys new file mode 100644 index 000000000..7ec2b0114 --- /dev/null +++ b/tests/ecp5/adffs.ys @@ -0,0 +1,10 @@ +read_verilog adffs.v +proc +async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 4 t:TRELLIS_FF +select -assert-count 7 t:LUT4 +select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D diff --git a/tests/ecp5/alu.v b/tests/ecp5/alu.v new file mode 100644 index 000000000..f82cc2e21 --- /dev/null +++ b/tests/ecp5/alu.v @@ -0,0 +1,19 @@ +module top ( + input clock, + input [31:0] dinA, dinB, + input [2:0] opcode, + output reg [31:0] dout +); + always @(posedge clock) begin + case (opcode) + 0: dout <= dinA + dinB; + 1: dout <= dinA - dinB; + 2: dout <= dinA >> dinB; + 3: dout <= $signed(dinA) >>> dinB; + 4: dout <= dinA << dinB; + 5: dout <= dinA & dinB; + 6: dout <= dinA | dinB; + 7: dout <= dinA ^ dinB; + endcase + end +endmodule diff --git a/tests/ecp5/alu.ys b/tests/ecp5/alu.ys new file mode 100644 index 000000000..bd859efc4 --- /dev/null +++ b/tests/ecp5/alu.ys @@ -0,0 +1,11 @@ +read_verilog alu.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 62 t:SB_CARRY +select -assert-count 32 t:SB_DFF +select -assert-count 655 t:SB_LUT4 +select -assert-none t:SB_CARRY t:SB_DFF t:SB_LUT4 %% t:* %D diff --git a/tests/ecp5/counter.v b/tests/ecp5/counter.v new file mode 100644 index 000000000..52852f8ac --- /dev/null +++ b/tests/ecp5/counter.v @@ -0,0 +1,17 @@ +module top (
+out,
+clk,
+reset
+);
+ output [7:0] out;
+ input clk, reset;
+ reg [7:0] out;
+
+ always @(posedge clk, posedge reset)
+ if (reset) begin
+ out <= 8'b0 ;
+ end else
+ out <= out + 1;
+
+
+endmodule
diff --git a/tests/ecp5/counter.ys b/tests/ecp5/counter.ys new file mode 100644 index 000000000..c65c21622 --- /dev/null +++ b/tests/ecp5/counter.ys @@ -0,0 +1,11 @@ +read_verilog counter.v +hierarchy -top top +proc +flatten +equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 6 t:SB_CARRY +select -assert-count 8 t:SB_DFFR +select -assert-count 8 t:SB_LUT4 +select -assert-none t:SB_CARRY t:SB_DFFR t:SB_LUT4 %% t:* %D diff --git a/tests/ecp5/dffs.v b/tests/ecp5/dffs.v new file mode 100644 index 000000000..d97840c43 --- /dev/null +++ b/tests/ecp5/dffs.v @@ -0,0 +1,37 @@ +module dff + ( input d, clk, output reg q ); + always @( posedge clk ) + q <= d; +endmodule + +module dffe + ( input d, clk, en, output reg q ); + initial begin + q = 0; + end + always @( posedge clk ) + if ( en ) + q <= d; +endmodule + +module top ( +input clk, +input en, +input a, +output b,b1, +); + +dff u_dff ( + .clk (clk ), + .d (a ), + .q (b ) + ); + +dffe u_ndffe ( + .clk (clk ), + .en (en), + .d (a ), + .q (b1 ) + ); + +endmodule diff --git a/tests/ecp5/dffs.ys b/tests/ecp5/dffs.ys new file mode 100644 index 000000000..5510bb440 --- /dev/null +++ b/tests/ecp5/dffs.ys @@ -0,0 +1,9 @@ +read_verilog dffs.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 2 t:TRELLIS_FF +select -assert-none t:TRELLIS_FF %% t:* %D diff --git a/tests/ecp5/div_mod.v b/tests/ecp5/div_mod.v new file mode 100644 index 000000000..64a36707d --- /dev/null +++ b/tests/ecp5/div_mod.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x % y; +assign B = x / y; + +endmodule diff --git a/tests/ecp5/div_mod.ys b/tests/ecp5/div_mod.ys new file mode 100644 index 000000000..fb13be5d5 --- /dev/null +++ b/tests/ecp5/div_mod.ys @@ -0,0 +1,12 @@ +read_verilog div_mod.v +hierarchy -top top +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 28 t:CCU2C +select -assert-count 48 t:L6MUX21 +select -assert-count 194 t:LUT4 +select -assert-count 84 t:PFUMX +select -assert-none t:LUT4 t:CCU2C t:L6MUX21 t:PFUMX %% t:* %D diff --git a/tests/ecp5/dpram.v b/tests/ecp5/dpram.v new file mode 100644 index 000000000..3ea4c1f27 --- /dev/null +++ b/tests/ecp5/dpram.v @@ -0,0 +1,23 @@ +/* +Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 72]. +*/ +module top (din, write_en, waddr, wclk, raddr, rclk, dout); +parameter addr_width = 8; +parameter data_width = 8; +input [addr_width-1:0] waddr, raddr; +input [data_width-1:0] din; +input write_en, wclk, rclk; +output [data_width-1:0] dout; +reg [data_width-1:0] dout; +reg [data_width-1:0] mem [(1<<addr_width)-1:0] +/* synthesis syn_ramstyle = "no_rw_check" */ ; +always @(posedge wclk) // Write memory. +begin +if (write_en) +mem[waddr] <= din; // Using write address bus. +end +always @(posedge rclk) // Read memory. +begin +dout <= mem[raddr]; // Using read address bus. +end +endmodule diff --git a/tests/ecp5/dpram.ys b/tests/ecp5/dpram.ys new file mode 100644 index 000000000..b88eb80dd --- /dev/null +++ b/tests/ecp5/dpram.ys @@ -0,0 +1,18 @@ +read_verilog dpram.v +hierarchy -top top +proc +memory -nomap +equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5 +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter + +#ERROR: Failed to import cell gate.mem.0.0.0 (type DP16KD) to SAT database. +#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd top +select -assert-count 1 t:DP16KD +select -assert-none t:DP16KD %% t:* %D +write_verilog dpram_synth.v diff --git a/tests/ecp5/dpram_synth.v b/tests/ecp5/dpram_synth.v new file mode 100644 index 000000000..7ae20bbba --- /dev/null +++ b/tests/ecp5/dpram_synth.v @@ -0,0 +1,165 @@ +/* Generated by Yosys 0.9+36 (git sha1 7e8f7f4c, gcc 8.3.0-6ubuntu1 -Og -fPIC) */ + +(* dynports = 1 *) +(* top = 1 *) +(* src = "dpram.v:4" *) +module top(din, write_en, waddr, wclk, raddr, rclk, dout); + (* unused_bits = "8" *) + wire [8:0] _0_; + (* src = "dpram.v:8" *) + input [7:0] din; + (* src = "dpram.v:10" *) + output [7:0] dout; + (* src = "dpram.v:7" *) + input [7:0] raddr; + (* src = "dpram.v:9" *) + input rclk; + (* src = "dpram.v:7" *) + input [7:0] waddr; + (* src = "dpram.v:9" *) + input wclk; + (* src = "dpram.v:9" *) + input write_en; + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/brams_map.v:79" *) + DP16KD #( + .CLKAMUX("CLKA"), + .CLKBMUX("CLKB"), + .DATA_WIDTH_A(32'sd9), + .DATA_WIDTH_B(32'sd9), + .GSR("DISABLED"), + .INITVAL_00(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_01(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_02(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_03(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_04(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_05(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_06(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_07(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_08(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_09(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_0A(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_0B(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_0C(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_0D(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_0E(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_0F(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_10(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_11(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_12(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_13(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_14(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_15(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_16(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_17(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_18(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_19(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_1A(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_1B(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_1C(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_1D(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_1E(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_1F(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_20(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_21(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_22(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_23(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_24(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_25(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_26(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_27(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_28(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_29(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_2A(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_2B(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_2C(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_2D(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_2E(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_2F(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_30(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_31(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_32(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_33(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_34(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_35(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_36(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_37(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_38(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_39(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_3A(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_3B(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_3C(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_3D(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_3E(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .INITVAL_3F(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), + .WRITEMODE_A("READBEFOREWRITE"), + .WRITEMODE_B("READBEFOREWRITE") + ) \mem.0.0.0 ( + .ADA0(1'h0), + .ADA1(1'h0), + .ADA10(waddr[7]), + .ADA11(1'h0), + .ADA12(1'h0), + .ADA13(1'h0), + .ADA2(1'h0), + .ADA3(waddr[0]), + .ADA4(waddr[1]), + .ADA5(waddr[2]), + .ADA6(waddr[3]), + .ADA7(waddr[4]), + .ADA8(waddr[5]), + .ADA9(waddr[6]), + .ADB0(1'h0), + .ADB1(1'h0), + .ADB10(raddr[7]), + .ADB11(1'h0), + .ADB12(1'h0), + .ADB13(1'h0), + .ADB2(1'h0), + .ADB3(raddr[0]), + .ADB4(raddr[1]), + .ADB5(raddr[2]), + .ADB6(raddr[3]), + .ADB7(raddr[4]), + .ADB8(raddr[5]), + .ADB9(raddr[6]), + .CEA(1'h1), + .CEB(1'h1), + .CLKA(wclk), + .CLKB(rclk), + .DIA0(din[0]), + .DIA1(din[1]), + .DIA10(1'h0), + .DIA11(1'h0), + .DIA12(1'h0), + .DIA13(1'h0), + .DIA14(1'h0), + .DIA15(1'h0), + .DIA16(1'h0), + .DIA17(1'h0), + .DIA2(din[2]), + .DIA3(din[3]), + .DIA4(din[4]), + .DIA5(din[5]), + .DIA6(din[6]), + .DIA7(din[7]), + .DIA8(1'h0), + .DIA9(1'h0), + .DOB0(dout[0]), + .DOB1(dout[1]), + .DOB2(dout[2]), + .DOB3(dout[3]), + .DOB4(dout[4]), + .DOB5(dout[5]), + .DOB6(dout[6]), + .DOB7(dout[7]), + .DOB8(_0_[8]), + .OCEA(1'h1), + .OCEB(1'h1), + .RSTA(1'h0), + .RSTB(1'h0), + .WEA(write_en), + .WEB(1'h0) + ); + assign _0_[7:0] = dout; +endmodule diff --git a/tests/ecp5/fsm.v b/tests/ecp5/fsm.v new file mode 100644 index 000000000..0605bd102 --- /dev/null +++ b/tests/ecp5/fsm.v @@ -0,0 +1,73 @@ + module fsm (
+ clock,
+ reset,
+ req_0,
+ req_1,
+ gnt_0,
+ gnt_1
+ );
+ input clock,reset,req_0,req_1;
+ output gnt_0,gnt_1;
+ wire clock,reset,req_0,req_1;
+ reg gnt_0,gnt_1;
+
+ parameter SIZE = 3 ;
+ parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
+
+ reg [SIZE-1:0] state;
+ reg [SIZE-1:0] next_state;
+
+ always @ (posedge clock)
+ begin : FSM
+ if (reset == 1'b1) begin
+ state <= #1 IDLE;
+ gnt_0 <= 0;
+ gnt_1 <= 0;
+ end else
+ case(state)
+ IDLE : if (req_0 == 1'b1) begin
+ state <= #1 GNT0;
+ gnt_0 <= 1;
+ end else if (req_1 == 1'b1) begin
+ gnt_1 <= 1;
+ state <= #1 GNT0;
+ end else begin
+ state <= #1 IDLE;
+ end
+ GNT0 : if (req_0 == 1'b1) begin
+ state <= #1 GNT0;
+ end else begin
+ gnt_0 <= 0;
+ state <= #1 IDLE;
+ end
+ GNT1 : if (req_1 == 1'b1) begin
+ state <= #1 GNT2;
+ gnt_1 <= req_0;
+ end
+ GNT2 : if (req_0 == 1'b1) begin
+ state <= #1 GNT1;
+ gnt_1 <= req_1;
+ end
+ default : state <= #1 IDLE;
+ endcase
+ end
+
+ endmodule
+
+ module top (
+input clk,
+input rst,
+input a,
+input b,
+output g0,
+output g1
+);
+
+fsm u_fsm ( .clock(clk),
+ .reset(rst),
+ .req_0(a),
+ .req_1(b),
+ .gnt_0(g0),
+ .gnt_1(g1));
+
+endmodule
diff --git a/tests/ecp5/fsm.ys b/tests/ecp5/fsm.ys new file mode 100644 index 000000000..4cc8629d6 --- /dev/null +++ b/tests/ecp5/fsm.ys @@ -0,0 +1,13 @@ +read_verilog fsm.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 2 t:SB_DFFESR +select -assert-count 2 t:SB_DFFSR +select -assert-count 1 t:SB_DFFSS +select -assert-count 13 t:SB_LUT4 +select -assert-none t:SB_DFFESR t:SB_DFFSR t:SB_DFFSS t:SB_LUT4 %% t:* %D diff --git a/tests/ecp5/latches.v b/tests/ecp5/latches.v new file mode 100644 index 000000000..9dc43e4c2 --- /dev/null +++ b/tests/ecp5/latches.v @@ -0,0 +1,58 @@ +module latchp + ( input d, clk, en, output reg q ); + always @* + if ( en ) + q <= d; +endmodule + +module latchn + ( input d, clk, en, output reg q ); + always @* + if ( !en ) + q <= d; +endmodule + +module latchsr + ( input d, clk, en, clr, pre, output reg q ); + always @* + if ( clr ) + q <= 1'b0; + else if ( pre ) + q <= 1'b1; + else if ( en ) + q <= d; +endmodule + + +module top ( +input clk, +input clr, +input pre, +input a, +output b,b1,b2 +); + + +latchp u_latchp ( + .en (clk ), + .d (a ), + .q (b ) + ); + + +latchn u_latchn ( + .en (clk ), + .d (a ), + .q (b1 ) + ); + + +latchsr u_latchsr ( + .en (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b2 ) + ); + +endmodule diff --git a/tests/ecp5/latches.ys b/tests/ecp5/latches.ys new file mode 100644 index 000000000..6eaf77cfd --- /dev/null +++ b/tests/ecp5/latches.ys @@ -0,0 +1,17 @@ +read_verilog latches.v +design -save read + +proc +async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock +flatten +synth_ecp5 +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) + +design -load read +synth_ecp5 +cd top +select -assert-count 4 t:LUT4 +select -assert-count 1 t:PFUMX +select -assert-none t:LUT4 t:PFUMX %% t:* %D +write_verilog latches_synth.v diff --git a/tests/ecp5/latches_synth.v b/tests/ecp5/latches_synth.v new file mode 100644 index 000000000..816e10d4d --- /dev/null +++ b/tests/ecp5/latches_synth.v @@ -0,0 +1,109 @@ +/* Generated by Yosys 0.9+36 (git sha1 7e8f7f4c, gcc 8.3.0-6ubuntu1 -Og -fPIC) */ + +(* top = 1 *) +(* src = "latches.v:27" *) +module top(clk, clr, pre, a, b, b1, b2); + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:105" *) + wire _0_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:105" *) + wire _1_; + (* src = "latches.v:31" *) + input a; + (* src = "latches.v:32" *) + output b; + (* src = "latches.v:32" *) + output b1; + (* src = "latches.v:32" *) + output b2; + (* src = "latches.v:28" *) + input clk; + (* src = "latches.v:29" *) + input clr; + (* src = "latches.v:30" *) + input pre; + (* src = "latches.v:43|latches.v:9" *) + wire \u_latchn.d ; + (* src = "latches.v:43|latches.v:9" *) + wire \u_latchn.en ; + (* src = "latches.v:43|latches.v:9" *) + wire \u_latchn.q ; + (* src = "latches.v:36|latches.v:2" *) + wire \u_latchp.d ; + (* src = "latches.v:36|latches.v:2" *) + wire \u_latchp.en ; + (* src = "latches.v:36|latches.v:2" *) + wire \u_latchp.q ; + (* src = "latches.v:50|latches.v:16" *) + wire \u_latchsr.clr ; + (* src = "latches.v:50|latches.v:16" *) + wire \u_latchsr.d ; + (* src = "latches.v:50|latches.v:16" *) + wire \u_latchsr.en ; + (* src = "latches.v:50|latches.v:16" *) + wire \u_latchsr.pre ; + (* src = "latches.v:50|latches.v:16" *) + wire \u_latchsr.q ; + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:106" *) + LUT4 #( + .INIT(16'h5150) + ) _2_ ( + .A(clr), + .B(clk), + .C(pre), + .D(b2), + .Z(_0_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:108" *) + LUT4 #( + .INIT(16'h5554) + ) _3_ ( + .A(clr), + .B(clk), + .C(pre), + .D(b2), + .Z(_1_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:110" *) + PFUMX _4_ ( + .ALUT(_1_), + .BLUT(_0_), + .C0(a), + .Z(b2) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:96" *) + LUT4 #( + .INIT(16'bx1x1x1x0x0x1x0x0) + ) _5_ ( + .A(1'h0), + .B(clk), + .C(b), + .D(a), + .Z(b) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:96" *) + LUT4 #( + .INIT(16'bx1x1x0x1x1x0x0x0) + ) _6_ ( + .A(1'h0), + .B(clk), + .C(b1), + .D(a), + .Z(b1) + ); + assign \u_latchn.d = a; + assign \u_latchn.en = clk; + assign \u_latchn.q = b1; + assign \u_latchp.d = a; + assign \u_latchp.en = clk; + assign \u_latchp.q = b; + assign \u_latchsr.clr = clr; + assign \u_latchsr.d = a; + assign \u_latchsr.en = clk; + assign \u_latchsr.pre = pre; + assign \u_latchsr.q = b2; +endmodule diff --git a/tests/ecp5/logic.v b/tests/ecp5/logic.v new file mode 100644 index 000000000..e5343cae0 --- /dev/null +++ b/tests/ecp5/logic.v @@ -0,0 +1,18 @@ +module top +( + input [0:7] in, + output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10 + ); + + assign B1 = in[0] & in[1]; + assign B2 = in[0] | in[1]; + assign B3 = in[0] ~& in[1]; + assign B4 = in[0] ~| in[1]; + assign B5 = in[0] ^ in[1]; + assign B6 = in[0] ~^ in[1]; + assign B7 = ~in[0]; + assign B8 = in[0]; + assign B9 = in[0:1] && in [2:3]; + assign B10 = in[0:1] || in [2:3]; + +endmodule diff --git a/tests/ecp5/logic.ys b/tests/ecp5/logic.ys new file mode 100644 index 000000000..fc5e5b1d8 --- /dev/null +++ b/tests/ecp5/logic.ys @@ -0,0 +1,7 @@ +read_verilog logic.v +hierarchy -top top +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 9 t:SB_LUT4 +select -assert-none t:SB_LUT4 %% t:* %D diff --git a/tests/ecp5/macc.v b/tests/ecp5/macc.v new file mode 100644 index 000000000..63a3d3a74 --- /dev/null +++ b/tests/ecp5/macc.v @@ -0,0 +1,25 @@ +/* +Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 77]. +*/ +module top(clk,a,b,c,set); +parameter A_WIDTH = 4; +parameter B_WIDTH = 3; +input set; +input clk; +input signed [(A_WIDTH - 1):0] a; +input signed [(B_WIDTH - 1):0] b; +output signed [(A_WIDTH + B_WIDTH - 1):0] c; +reg [(A_WIDTH + B_WIDTH - 1):0] reg_tmp_c; +assign c = reg_tmp_c; +always @(posedge clk) +begin +if(set) +begin +reg_tmp_c <= 0; +end +else +begin +reg_tmp_c <= a * b + c; +end +end +endmodule diff --git a/tests/ecp5/macc.ys b/tests/ecp5/macc.ys new file mode 100644 index 000000000..bc6340509 --- /dev/null +++ b/tests/ecp5/macc.ys @@ -0,0 +1,15 @@ +read_verilog macc.v +proc +hierarchy -top top +#Failed because of 14 unproven cells. +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +#equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 4 t:CCU2C +select -assert-count 6 t:L6MUX21 +select -assert-count 49 t:LUT4 +select -assert-count 19 t:PFUMX +select -assert-count 7 t:TRELLIS_FF + +select -assert-none t:CCU2C t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_FF %% t:* %D diff --git a/tests/ecp5/memory.v b/tests/ecp5/memory.v new file mode 100644 index 000000000..cb7753f7b --- /dev/null +++ b/tests/ecp5/memory.v @@ -0,0 +1,21 @@ +module top +( + input [7:0] data_a, + input [6:1] addr_a, + input we_a, clk, + output reg [7:0] q_a +); + // Declare the RAM variable + reg [7:0] ram[63:0]; + + // Port A + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + q_a <= data_a; + end + q_a <= ram[addr_a]; + end +endmodule diff --git a/tests/ecp5/memory.ys b/tests/ecp5/memory.ys new file mode 100644 index 000000000..c90f1991e --- /dev/null +++ b/tests/ecp5/memory.ys @@ -0,0 +1,21 @@ +read_verilog memory.v +hierarchy -top top +proc +memory -nomap +equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5 +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#ERROR: Called with -verify and proof did fail! +#sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd top +select -assert-count 24 t:L6MUX21 +select -assert-count 71 t:LUT4 +select -assert-count 32 t:PFUMX +select -assert-count 8 t:TRELLIS_DPR16X4 +select -assert-count 35 t:TRELLIS_FF +select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D +write_verilog memory_synth.v diff --git a/tests/ecp5/memory_synth.v b/tests/ecp5/memory_synth.v new file mode 100644 index 000000000..a6172de61 --- /dev/null +++ b/tests/ecp5/memory_synth.v @@ -0,0 +1,2121 @@ +/* Generated by Yosys 0.9+36 (git sha1 7e8f7f4c, gcc 8.3.0-6ubuntu1 -Og -fPIC) */ + +(* top = 1 *) +(* src = "memory.v:1" *) +module top(data_a, addr_a, we_a, clk, q_a); + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _000_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _001_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _002_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _003_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _004_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _005_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _006_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _007_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _008_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _009_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _010_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _011_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _012_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _013_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _014_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _015_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _016_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _017_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _018_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _019_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _020_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _021_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _022_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _023_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _024_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _025_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _026_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _027_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _028_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _029_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _030_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _031_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _032_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _033_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _034_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _035_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _036_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _037_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _038_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _039_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _040_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _041_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _042_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _043_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _044_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _045_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _046_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _047_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _048_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _049_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _050_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _051_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _052_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _053_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _054_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _055_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _056_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _057_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _058_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _059_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _060_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _061_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _062_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _063_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _064_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _065_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _066_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _067_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _068_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _069_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _070_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _071_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _072_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _073_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _074_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _075_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _076_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _077_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _078_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _079_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _080_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _081_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _082_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _083_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _084_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _085_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _086_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _087_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _088_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _089_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _090_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _091_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _092_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _093_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _094_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _095_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _096_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _097_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _098_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _099_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _100_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _101_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _102_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _103_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _104_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _105_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _106_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _107_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _108_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _109_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _110_; + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) + wire _111_; + wire _112_; + wire _113_; + wire _114_; + wire _115_; + wire _116_; + wire _117_; + wire _118_; + wire _119_; + wire _120_; + wire _121_; + wire _122_; + wire _123_; + wire _124_; + wire _125_; + wire _126_; + wire _127_; + wire _128_; + wire _129_; + wire _130_; + wire _131_; + wire _132_; + wire _133_; + wire _134_; + wire _135_; + wire _136_; + wire _137_; + wire _138_; + wire _139_; + wire _140_; + wire _141_; + wire _142_; + wire _143_; + wire _144_; + wire _145_; + wire _146_; + wire _147_; + wire _148_; + wire _149_; + wire _150_; + wire _151_; + wire _152_; + wire _153_; + wire [3:0] _154_; + wire [3:0] _155_; + wire [3:0] _156_; + wire [3:0] _157_; + wire [3:0] _158_; + wire [3:0] _159_; + wire [3:0] _160_; + wire [3:0] _161_; + (* src = "memory.v:4" *) + input [6:1] addr_a; + (* src = "memory.v:5" *) + input clk; + (* src = "memory.v:3" *) + input [7:0] data_a; + (* src = "memory.v:6" *) + output [7:0] q_a; + (* src = "memory.v:5" *) + input we_a; + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:92" *) + LUT4 #( + .INIT(16'bxxx0xxx0xxx0xxx1) + ) _162_ ( + .A(1'h0), + .B(1'h0), + .C(addr_a[5]), + .D(addr_a[6]), + .Z(_147_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:92" *) + LUT4 #( + .INIT(16'bxxx0xxx0xxx1xxx0) + ) _163_ ( + .A(1'h0), + .B(1'h0), + .C(addr_a[5]), + .D(addr_a[6]), + .Z(_148_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:92" *) + LUT4 #( + .INIT(16'bxxx0xxx0xxx1xxx0) + ) _164_ ( + .A(1'h0), + .B(1'h0), + .C(addr_a[6]), + .D(addr_a[5]), + .Z(_149_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:96" *) + LUT4 #( + .INIT(16'bx1x0x0x0x0x0x0x0) + ) _165_ ( + .A(1'h0), + .B(we_a), + .C(addr_a[5]), + .D(addr_a[6]), + .Z(_153_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:96" *) + LUT4 #( + .INIT(16'bx0x0x0x0x0x0x1x0) + ) _166_ ( + .A(1'h0), + .B(we_a), + .C(addr_a[5]), + .D(addr_a[6]), + .Z(_150_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:96" *) + LUT4 #( + .INIT(16'bx0x0x0x0x1x0x0x0) + ) _167_ ( + .A(1'h0), + .B(we_a), + .C(addr_a[5]), + .D(addr_a[6]), + .Z(_151_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:96" *) + LUT4 #( + .INIT(16'bx0x0x0x0x1x0x0x0) + ) _168_ ( + .A(1'h0), + .B(we_a), + .C(addr_a[6]), + .D(addr_a[5]), + .Z(_152_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:130" *) + LUT4 #( + .INIT(16'hf000) + ) _169_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_136_), + .Z(_000_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:132" *) + LUT4 #( + .INIT(16'hfccc) + ) _170_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_136_), + .Z(_001_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:135" *) + LUT4 #( + .INIT(16'hfaaa) + ) _171_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_136_), + .Z(_002_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:137" *) + LUT4 #( + .INIT(16'hfeee) + ) _172_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_136_), + .Z(_003_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:140" *) + LUT4 #( + .INIT(16'hf101) + ) _173_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_136_), + .Z(_004_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:142" *) + LUT4 #( + .INIT(16'hfdcd) + ) _174_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_136_), + .Z(_005_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:145" *) + LUT4 #( + .INIT(16'hfbab) + ) _175_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_136_), + .Z(_006_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:147" *) + LUT4 #( + .INIT(16'hffef) + ) _176_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_136_), + .Z(_007_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:150" *) + PFUMX _177_ ( + .ALUT(_001_), + .BLUT(_000_), + .C0(_132_), + .Z(_008_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:151" *) + PFUMX _178_ ( + .ALUT(_003_), + .BLUT(_002_), + .C0(_132_), + .Z(_009_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:152" *) + PFUMX _179_ ( + .ALUT(_005_), + .BLUT(_004_), + .C0(_132_), + .Z(_010_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:153" *) + PFUMX _180_ ( + .ALUT(_007_), + .BLUT(_006_), + .C0(_132_), + .Z(_011_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:154" *) + L6MUX21 _181_ ( + .D0(_008_), + .D1(_009_), + .SD(_128_), + .Z(_012_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:155" *) + L6MUX21 _182_ ( + .D0(_010_), + .D1(_011_), + .SD(_128_), + .Z(_013_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:156" *) + L6MUX21 _183_ ( + .D0(_012_), + .D1(_013_), + .SD(_140_), + .Z(q_a[4]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:130" *) + LUT4 #( + .INIT(16'hf000) + ) _184_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_137_), + .Z(_014_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:132" *) + LUT4 #( + .INIT(16'hfccc) + ) _185_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_137_), + .Z(_015_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:135" *) + LUT4 #( + .INIT(16'hfaaa) + ) _186_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_137_), + .Z(_016_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:137" *) + LUT4 #( + .INIT(16'hfeee) + ) _187_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_137_), + .Z(_017_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:140" *) + LUT4 #( + .INIT(16'hf101) + ) _188_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_137_), + .Z(_018_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:142" *) + LUT4 #( + .INIT(16'hfdcd) + ) _189_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_137_), + .Z(_019_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:145" *) + LUT4 #( + .INIT(16'hfbab) + ) _190_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_137_), + .Z(_020_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:147" *) + LUT4 #( + .INIT(16'hffef) + ) _191_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_137_), + .Z(_021_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:150" *) + PFUMX _192_ ( + .ALUT(_015_), + .BLUT(_014_), + .C0(_133_), + .Z(_022_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:151" *) + PFUMX _193_ ( + .ALUT(_017_), + .BLUT(_016_), + .C0(_133_), + .Z(_023_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:152" *) + PFUMX _194_ ( + .ALUT(_019_), + .BLUT(_018_), + .C0(_133_), + .Z(_024_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:153" *) + PFUMX _195_ ( + .ALUT(_021_), + .BLUT(_020_), + .C0(_133_), + .Z(_025_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:154" *) + L6MUX21 _196_ ( + .D0(_022_), + .D1(_023_), + .SD(_129_), + .Z(_026_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:155" *) + L6MUX21 _197_ ( + .D0(_024_), + .D1(_025_), + .SD(_129_), + .Z(_027_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:156" *) + L6MUX21 _198_ ( + .D0(_026_), + .D1(_027_), + .SD(_141_), + .Z(q_a[5]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:130" *) + LUT4 #( + .INIT(16'hf000) + ) _199_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_138_), + .Z(_028_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:132" *) + LUT4 #( + .INIT(16'hfccc) + ) _200_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_138_), + .Z(_029_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:135" *) + LUT4 #( + .INIT(16'hfaaa) + ) _201_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_138_), + .Z(_030_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:137" *) + LUT4 #( + .INIT(16'hfeee) + ) _202_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_138_), + .Z(_031_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:140" *) + LUT4 #( + .INIT(16'hf101) + ) _203_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_138_), + .Z(_032_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:142" *) + LUT4 #( + .INIT(16'hfdcd) + ) _204_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_138_), + .Z(_033_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:145" *) + LUT4 #( + .INIT(16'hfbab) + ) _205_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_138_), + .Z(_034_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:147" *) + LUT4 #( + .INIT(16'hffef) + ) _206_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_138_), + .Z(_035_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:150" *) + PFUMX _207_ ( + .ALUT(_029_), + .BLUT(_028_), + .C0(_134_), + .Z(_036_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:151" *) + PFUMX _208_ ( + .ALUT(_031_), + .BLUT(_030_), + .C0(_134_), + .Z(_037_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:152" *) + PFUMX _209_ ( + .ALUT(_033_), + .BLUT(_032_), + .C0(_134_), + .Z(_038_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:153" *) + PFUMX _210_ ( + .ALUT(_035_), + .BLUT(_034_), + .C0(_134_), + .Z(_039_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:154" *) + L6MUX21 _211_ ( + .D0(_036_), + .D1(_037_), + .SD(_130_), + .Z(_040_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:155" *) + L6MUX21 _212_ ( + .D0(_038_), + .D1(_039_), + .SD(_130_), + .Z(_041_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:156" *) + L6MUX21 _213_ ( + .D0(_040_), + .D1(_041_), + .SD(_142_), + .Z(q_a[6]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:130" *) + LUT4 #( + .INIT(16'hf000) + ) _214_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_139_), + .Z(_042_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:132" *) + LUT4 #( + .INIT(16'hfccc) + ) _215_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_139_), + .Z(_043_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:135" *) + LUT4 #( + .INIT(16'hfaaa) + ) _216_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_139_), + .Z(_044_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:137" *) + LUT4 #( + .INIT(16'hfeee) + ) _217_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_139_), + .Z(_045_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:140" *) + LUT4 #( + .INIT(16'hf101) + ) _218_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_139_), + .Z(_046_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:142" *) + LUT4 #( + .INIT(16'hfdcd) + ) _219_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_139_), + .Z(_047_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:145" *) + LUT4 #( + .INIT(16'hfbab) + ) _220_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_139_), + .Z(_048_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:147" *) + LUT4 #( + .INIT(16'hffef) + ) _221_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_139_), + .Z(_049_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:150" *) + PFUMX _222_ ( + .ALUT(_043_), + .BLUT(_042_), + .C0(_135_), + .Z(_050_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:151" *) + PFUMX _223_ ( + .ALUT(_045_), + .BLUT(_044_), + .C0(_135_), + .Z(_051_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:152" *) + PFUMX _224_ ( + .ALUT(_047_), + .BLUT(_046_), + .C0(_135_), + .Z(_052_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:153" *) + PFUMX _225_ ( + .ALUT(_049_), + .BLUT(_048_), + .C0(_135_), + .Z(_053_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:154" *) + L6MUX21 _226_ ( + .D0(_050_), + .D1(_051_), + .SD(_131_), + .Z(_054_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:155" *) + L6MUX21 _227_ ( + .D0(_052_), + .D1(_053_), + .SD(_131_), + .Z(_055_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:156" *) + L6MUX21 _228_ ( + .D0(_054_), + .D1(_055_), + .SD(_143_), + .Z(q_a[7]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:130" *) + LUT4 #( + .INIT(16'hf000) + ) _229_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_120_), + .Z(_056_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:132" *) + LUT4 #( + .INIT(16'hfccc) + ) _230_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_120_), + .Z(_057_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:135" *) + LUT4 #( + .INIT(16'hfaaa) + ) _231_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_120_), + .Z(_058_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:137" *) + LUT4 #( + .INIT(16'hfeee) + ) _232_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_120_), + .Z(_059_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:140" *) + LUT4 #( + .INIT(16'hf101) + ) _233_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_120_), + .Z(_060_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:142" *) + LUT4 #( + .INIT(16'hfdcd) + ) _234_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_120_), + .Z(_061_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:145" *) + LUT4 #( + .INIT(16'hfbab) + ) _235_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_120_), + .Z(_062_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:147" *) + LUT4 #( + .INIT(16'hffef) + ) _236_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_120_), + .Z(_063_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:150" *) + PFUMX _237_ ( + .ALUT(_057_), + .BLUT(_056_), + .C0(_116_), + .Z(_064_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:151" *) + PFUMX _238_ ( + .ALUT(_059_), + .BLUT(_058_), + .C0(_116_), + .Z(_065_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:152" *) + PFUMX _239_ ( + .ALUT(_061_), + .BLUT(_060_), + .C0(_116_), + .Z(_066_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:153" *) + PFUMX _240_ ( + .ALUT(_063_), + .BLUT(_062_), + .C0(_116_), + .Z(_067_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:154" *) + L6MUX21 _241_ ( + .D0(_064_), + .D1(_065_), + .SD(_112_), + .Z(_068_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:155" *) + L6MUX21 _242_ ( + .D0(_066_), + .D1(_067_), + .SD(_112_), + .Z(_069_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:156" *) + L6MUX21 _243_ ( + .D0(_068_), + .D1(_069_), + .SD(_124_), + .Z(q_a[0]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:130" *) + LUT4 #( + .INIT(16'hf000) + ) _244_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_121_), + .Z(_070_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:132" *) + LUT4 #( + .INIT(16'hfccc) + ) _245_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_121_), + .Z(_071_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:135" *) + LUT4 #( + .INIT(16'hfaaa) + ) _246_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_121_), + .Z(_072_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:137" *) + LUT4 #( + .INIT(16'hfeee) + ) _247_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_121_), + .Z(_073_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:140" *) + LUT4 #( + .INIT(16'hf101) + ) _248_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_121_), + .Z(_074_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:142" *) + LUT4 #( + .INIT(16'hfdcd) + ) _249_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_121_), + .Z(_075_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:145" *) + LUT4 #( + .INIT(16'hfbab) + ) _250_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_121_), + .Z(_076_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:147" *) + LUT4 #( + .INIT(16'hffef) + ) _251_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_121_), + .Z(_077_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:150" *) + PFUMX _252_ ( + .ALUT(_071_), + .BLUT(_070_), + .C0(_117_), + .Z(_078_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:151" *) + PFUMX _253_ ( + .ALUT(_073_), + .BLUT(_072_), + .C0(_117_), + .Z(_079_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:152" *) + PFUMX _254_ ( + .ALUT(_075_), + .BLUT(_074_), + .C0(_117_), + .Z(_080_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:153" *) + PFUMX _255_ ( + .ALUT(_077_), + .BLUT(_076_), + .C0(_117_), + .Z(_081_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:154" *) + L6MUX21 _256_ ( + .D0(_078_), + .D1(_079_), + .SD(_113_), + .Z(_082_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:155" *) + L6MUX21 _257_ ( + .D0(_080_), + .D1(_081_), + .SD(_113_), + .Z(_083_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:156" *) + L6MUX21 _258_ ( + .D0(_082_), + .D1(_083_), + .SD(_125_), + .Z(q_a[1]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:130" *) + LUT4 #( + .INIT(16'hf000) + ) _259_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_122_), + .Z(_084_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:132" *) + LUT4 #( + .INIT(16'hfccc) + ) _260_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_122_), + .Z(_085_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:135" *) + LUT4 #( + .INIT(16'hfaaa) + ) _261_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_122_), + .Z(_086_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:137" *) + LUT4 #( + .INIT(16'hfeee) + ) _262_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_122_), + .Z(_087_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:140" *) + LUT4 #( + .INIT(16'hf101) + ) _263_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_122_), + .Z(_088_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:142" *) + LUT4 #( + .INIT(16'hfdcd) + ) _264_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_122_), + .Z(_089_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:145" *) + LUT4 #( + .INIT(16'hfbab) + ) _265_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_122_), + .Z(_090_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:147" *) + LUT4 #( + .INIT(16'hffef) + ) _266_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_122_), + .Z(_091_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:150" *) + PFUMX _267_ ( + .ALUT(_085_), + .BLUT(_084_), + .C0(_118_), + .Z(_092_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:151" *) + PFUMX _268_ ( + .ALUT(_087_), + .BLUT(_086_), + .C0(_118_), + .Z(_093_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:152" *) + PFUMX _269_ ( + .ALUT(_089_), + .BLUT(_088_), + .C0(_118_), + .Z(_094_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:153" *) + PFUMX _270_ ( + .ALUT(_091_), + .BLUT(_090_), + .C0(_118_), + .Z(_095_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:154" *) + L6MUX21 _271_ ( + .D0(_092_), + .D1(_093_), + .SD(_114_), + .Z(_096_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:155" *) + L6MUX21 _272_ ( + .D0(_094_), + .D1(_095_), + .SD(_114_), + .Z(_097_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:156" *) + L6MUX21 _273_ ( + .D0(_096_), + .D1(_097_), + .SD(_126_), + .Z(q_a[2]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:130" *) + LUT4 #( + .INIT(16'hf000) + ) _274_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_123_), + .Z(_098_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:132" *) + LUT4 #( + .INIT(16'hfccc) + ) _275_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_123_), + .Z(_099_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:135" *) + LUT4 #( + .INIT(16'hfaaa) + ) _276_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_123_), + .Z(_100_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:137" *) + LUT4 #( + .INIT(16'hfeee) + ) _277_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_123_), + .Z(_101_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:140" *) + LUT4 #( + .INIT(16'hf101) + ) _278_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_123_), + .Z(_102_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:142" *) + LUT4 #( + .INIT(16'hfdcd) + ) _279_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_123_), + .Z(_103_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:145" *) + LUT4 #( + .INIT(16'hfbab) + ) _280_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_123_), + .Z(_104_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:147" *) + LUT4 #( + .INIT(16'hffef) + ) _281_ ( + .A(_144_), + .B(_145_), + .C(_146_), + .D(_123_), + .Z(_105_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:150" *) + PFUMX _282_ ( + .ALUT(_099_), + .BLUT(_098_), + .C0(_119_), + .Z(_106_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:151" *) + PFUMX _283_ ( + .ALUT(_101_), + .BLUT(_100_), + .C0(_119_), + .Z(_107_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:152" *) + PFUMX _284_ ( + .ALUT(_103_), + .BLUT(_102_), + .C0(_119_), + .Z(_108_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:153" *) + PFUMX _285_ ( + .ALUT(_105_), + .BLUT(_104_), + .C0(_119_), + .Z(_109_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:154" *) + L6MUX21 _286_ ( + .D0(_106_), + .D1(_107_), + .SD(_115_), + .Z(_110_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:155" *) + L6MUX21 _287_ ( + .D0(_108_), + .D1(_109_), + .SD(_115_), + .Z(_111_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:156" *) + L6MUX21 _288_ ( + .D0(_110_), + .D1(_111_), + .SD(_127_), + .Z(q_a[3]) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _289_ ( + .CLK(clk), + .DI(_147_), + .LSR(1'h0), + .Q(_144_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _290_ ( + .CLK(clk), + .DI(_154_[0]), + .LSR(1'h0), + .Q(_112_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _291_ ( + .CLK(clk), + .DI(_154_[1]), + .LSR(1'h0), + .Q(_113_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _292_ ( + .CLK(clk), + .DI(_154_[2]), + .LSR(1'h0), + .Q(_114_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _293_ ( + .CLK(clk), + .DI(_154_[3]), + .LSR(1'h0), + .Q(_115_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _294_ ( + .CLK(clk), + .DI(_155_[0]), + .LSR(1'h0), + .Q(_116_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _295_ ( + .CLK(clk), + .DI(_155_[1]), + .LSR(1'h0), + .Q(_117_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _296_ ( + .CLK(clk), + .DI(_155_[2]), + .LSR(1'h0), + .Q(_118_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _297_ ( + .CLK(clk), + .DI(_155_[3]), + .LSR(1'h0), + .Q(_119_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _298_ ( + .CLK(clk), + .DI(_156_[0]), + .LSR(1'h0), + .Q(_120_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _299_ ( + .CLK(clk), + .DI(_156_[1]), + .LSR(1'h0), + .Q(_121_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _300_ ( + .CLK(clk), + .DI(_156_[2]), + .LSR(1'h0), + .Q(_122_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _301_ ( + .CLK(clk), + .DI(_156_[3]), + .LSR(1'h0), + .Q(_123_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _302_ ( + .CLK(clk), + .DI(_149_), + .LSR(1'h0), + .Q(_146_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _303_ ( + .CLK(clk), + .DI(_157_[0]), + .LSR(1'h0), + .Q(_124_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _304_ ( + .CLK(clk), + .DI(_157_[1]), + .LSR(1'h0), + .Q(_125_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _305_ ( + .CLK(clk), + .DI(_157_[2]), + .LSR(1'h0), + .Q(_126_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _306_ ( + .CLK(clk), + .DI(_157_[3]), + .LSR(1'h0), + .Q(_127_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _307_ ( + .CLK(clk), + .DI(_158_[0]), + .LSR(1'h0), + .Q(_128_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _308_ ( + .CLK(clk), + .DI(_158_[1]), + .LSR(1'h0), + .Q(_129_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _309_ ( + .CLK(clk), + .DI(_158_[2]), + .LSR(1'h0), + .Q(_130_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _310_ ( + .CLK(clk), + .DI(_158_[3]), + .LSR(1'h0), + .Q(_131_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _311_ ( + .CLK(clk), + .DI(_159_[0]), + .LSR(1'h0), + .Q(_132_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _312_ ( + .CLK(clk), + .DI(_159_[1]), + .LSR(1'h0), + .Q(_133_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _313_ ( + .CLK(clk), + .DI(_159_[2]), + .LSR(1'h0), + .Q(_134_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _314_ ( + .CLK(clk), + .DI(_159_[3]), + .LSR(1'h0), + .Q(_135_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _315_ ( + .CLK(clk), + .DI(_148_), + .LSR(1'h0), + .Q(_145_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _316_ ( + .CLK(clk), + .DI(_160_[0]), + .LSR(1'h0), + .Q(_136_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _317_ ( + .CLK(clk), + .DI(_160_[1]), + .LSR(1'h0), + .Q(_137_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _318_ ( + .CLK(clk), + .DI(_160_[2]), + .LSR(1'h0), + .Q(_138_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _319_ ( + .CLK(clk), + .DI(_160_[3]), + .LSR(1'h0), + .Q(_139_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _320_ ( + .CLK(clk), + .DI(_161_[0]), + .LSR(1'h0), + .Q(_140_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _321_ ( + .CLK(clk), + .DI(_161_[1]), + .LSR(1'h0), + .Q(_141_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _322_ ( + .CLK(clk), + .DI(_161_[2]), + .LSR(1'h0), + .Q(_142_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) + TRELLIS_FF #( + .CEMUX("1"), + .CLKMUX("CLK"), + .GSR("DISABLED"), + .LSRMUX("LSR"), + .REGSET("RESET") + ) _323_ ( + .CLK(clk), + .DI(_161_[3]), + .LSR(1'h0), + .Q(_143_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/lutrams_map.v:15" *) + TRELLIS_DPR16X4 #( + .INITVAL(64'hxxxxxxxxxxxxxxxx), + .WCKMUX("WCK"), + .WREMUX("WRE") + ) \ram.0.0.0 ( + .DI(data_a[3:0]), + .DO(_154_), + .RAD(addr_a[4:1]), + .WAD(addr_a[4:1]), + .WCK(clk), + .WRE(_150_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/lutrams_map.v:15" *) + TRELLIS_DPR16X4 #( + .INITVAL(64'hxxxxxxxxxxxxxxxx), + .WCKMUX("WCK"), + .WREMUX("WRE") + ) \ram.0.1.0 ( + .DI(data_a[3:0]), + .DO(_155_), + .RAD(addr_a[4:1]), + .WAD(addr_a[4:1]), + .WCK(clk), + .WRE(_151_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/lutrams_map.v:15" *) + TRELLIS_DPR16X4 #( + .INITVAL(64'hxxxxxxxxxxxxxxxx), + .WCKMUX("WCK"), + .WREMUX("WRE") + ) \ram.0.2.0 ( + .DI(data_a[3:0]), + .DO(_156_), + .RAD(addr_a[4:1]), + .WAD(addr_a[4:1]), + .WCK(clk), + .WRE(_152_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/lutrams_map.v:15" *) + TRELLIS_DPR16X4 #( + .INITVAL(64'hxxxxxxxxxxxxxxxx), + .WCKMUX("WCK"), + .WREMUX("WRE") + ) \ram.0.3.0 ( + .DI(data_a[3:0]), + .DO(_157_), + .RAD(addr_a[4:1]), + .WAD(addr_a[4:1]), + .WCK(clk), + .WRE(_153_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/lutrams_map.v:15" *) + TRELLIS_DPR16X4 #( + .INITVAL(64'hxxxxxxxxxxxxxxxx), + .WCKMUX("WCK"), + .WREMUX("WRE") + ) \ram.1.0.0 ( + .DI(data_a[7:4]), + .DO(_158_), + .RAD(addr_a[4:1]), + .WAD(addr_a[4:1]), + .WCK(clk), + .WRE(_150_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/lutrams_map.v:15" *) + TRELLIS_DPR16X4 #( + .INITVAL(64'hxxxxxxxxxxxxxxxx), + .WCKMUX("WCK"), + .WREMUX("WRE") + ) \ram.1.1.0 ( + .DI(data_a[7:4]), + .DO(_159_), + .RAD(addr_a[4:1]), + .WAD(addr_a[4:1]), + .WCK(clk), + .WRE(_151_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/lutrams_map.v:15" *) + TRELLIS_DPR16X4 #( + .INITVAL(64'hxxxxxxxxxxxxxxxx), + .WCKMUX("WCK"), + .WREMUX("WRE") + ) \ram.1.2.0 ( + .DI(data_a[7:4]), + .DO(_160_), + .RAD(addr_a[4:1]), + .WAD(addr_a[4:1]), + .WCK(clk), + .WRE(_152_) + ); + (* module_not_derived = 32'd1 *) + (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/lutrams_map.v:15" *) + TRELLIS_DPR16X4 #( + .INITVAL(64'hxxxxxxxxxxxxxxxx), + .WCKMUX("WCK"), + .WREMUX("WRE") + ) \ram.1.3.0 ( + .DI(data_a[7:4]), + .DO(_161_), + .RAD(addr_a[4:1]), + .WAD(addr_a[4:1]), + .WCK(clk), + .WRE(_153_) + ); +endmodule diff --git a/tests/ecp5/mul.v b/tests/ecp5/mul.v new file mode 100644 index 000000000..d5b48b1d7 --- /dev/null +++ b/tests/ecp5/mul.v @@ -0,0 +1,11 @@ +module top +( + input [5:0] x, + input [5:0] y, + + output [11:0] A, + ); + +assign A = x * y; + +endmodule diff --git a/tests/ecp5/mul.ys b/tests/ecp5/mul.ys new file mode 100644 index 000000000..0e8d6908f --- /dev/null +++ b/tests/ecp5/mul.ys @@ -0,0 +1,11 @@ +read_verilog mul.v +hierarchy -top top +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 6 t:CCU2C +select -assert-count 46 t:L6MUX21 +select -assert-count 169 t:LUT4 +select -assert-count 72 t:PFUMX + +select -assert-none t:CCU2C t:L6MUX21 t:LUT4 t:PFUMX %% t:* %D diff --git a/tests/ecp5/mux.v b/tests/ecp5/mux.v new file mode 100644 index 000000000..0814b733e --- /dev/null +++ b/tests/ecp5/mux.v @@ -0,0 +1,100 @@ +module mux2 (S,A,B,Y); + input S; + input A,B; + output reg Y; + + always @(*) + Y = (S)? B : A; +endmodule + +module mux4 ( S, D, Y ); + +input[1:0] S; +input[3:0] D; +output Y; + +reg Y; +wire[1:0] S; +wire[3:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + endcase +end + +endmodule + +module mux8 ( S, D, Y ); + +input[2:0] S; +input[7:0] D; +output Y; + +reg Y; +wire[2:0] S; +wire[7:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + 4 : Y = D[4]; + 5 : Y = D[5]; + 6 : Y = D[6]; + 7 : Y = D[7]; + endcase +end + +endmodule + +module mux16 (D, S, Y); + input [15:0] D; + input [3:0] S; + output Y; + +assign Y = D[S]; + +endmodule + + +module top ( +input [3:0] S, +input [15:0] D, +output M2,M4,M8,M16 +); + +mux2 u_mux2 ( + .S (S[0]), + .A (D[0]), + .B (D[1]), + .Y (M2) + ); + + +mux4 u_mux4 ( + .S (S[1:0]), + .D (D[3:0]), + .Y (M4) + ); + +mux8 u_mux8 ( + .S (S[2:0]), + .D (D[7:0]), + .Y (M8) + ); + +mux16 u_mux16 ( + .S (S[3:0]), + .D (D[15:0]), + .Y (M16) + ); + +endmodule diff --git a/tests/ecp5/mux.ys b/tests/ecp5/mux.ys new file mode 100644 index 000000000..7d40c9cf1 --- /dev/null +++ b/tests/ecp5/mux.ys @@ -0,0 +1,11 @@ +read_verilog mux.v +proc +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 32 t:LUT4 +select -assert-count 8 t:L6MUX21 +select -assert-count 14 t:PFUMX + +select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D diff --git a/tests/ecp5/rom.v b/tests/ecp5/rom.v new file mode 100644 index 000000000..0a0f41f37 --- /dev/null +++ b/tests/ecp5/rom.v @@ -0,0 +1,18 @@ +/* +Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 74]. +*/ +module top(data, addr); +output [3:0] data; +input [4:0] addr; +always @(addr) begin +case (addr) +0 : data = 'h4; +1 : data = 'h9; +2 : data = 'h1; +15 : data = 'h8; +16 : data = 'h1; +17 : data = 'h0; +default : data = 'h0; +endcase +end +endmodule diff --git a/tests/ecp5/rom.ys b/tests/ecp5/rom.ys new file mode 100644 index 000000000..8a52749a1 --- /dev/null +++ b/tests/ecp5/rom.ys @@ -0,0 +1,9 @@ +read_verilog rom.v +proc +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 6 t:LUT4 +select -assert-count 3 t:PFUMX +select -assert-none t:LUT4 t:PFUMX %% t:* %D diff --git a/tests/ecp5/run-test.sh b/tests/ecp5/run-test.sh new file mode 100755 index 000000000..2c72ca3a9 --- /dev/null +++ b/tests/ecp5/run-test.sh @@ -0,0 +1,20 @@ +#!/usr/bin/env bash +set -e +{ +echo "all::" +for x in *.ys; do + echo "all:: run-$x" + echo "run-$x:" + echo " @echo 'Running $x..'" + echo " @../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'" +done +for s in *.sh; do + if [ "$s" != "run-test.sh" ]; then + echo "all:: run-$s" + echo "run-$s:" + echo " @echo 'Running $s..'" + echo " @bash $s" + fi +done +} > run-test.mk +exec ${MAKE:-make} -f run-test.mk diff --git a/tests/ecp5/shifter.v b/tests/ecp5/shifter.v new file mode 100644 index 000000000..c55632552 --- /dev/null +++ b/tests/ecp5/shifter.v @@ -0,0 +1,22 @@ +module top (
+out,
+clk,
+in
+);
+ output [7:0] out;
+ input signed clk, in;
+ reg signed [7:0] out = 0;
+
+ always @(posedge clk)
+ begin
+`ifndef BUG
+ out <= out >> 1;
+ out[7] <= in;
+`else
+
+ out <= out << 1;
+ out[7] <= in;
+`endif
+ end
+
+endmodule
diff --git a/tests/ecp5/shifter.ys b/tests/ecp5/shifter.ys new file mode 100644 index 000000000..47d95d298 --- /dev/null +++ b/tests/ecp5/shifter.ys @@ -0,0 +1,9 @@ +read_verilog shifter.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 8 t:SB_DFF +select -assert-none t:SB_DFF %% t:* %D diff --git a/tests/ecp5/tribuf.v b/tests/ecp5/tribuf.v new file mode 100644 index 000000000..870a02584 --- /dev/null +++ b/tests/ecp5/tribuf.v @@ -0,0 +1,23 @@ +module tristate (en, i, o); + input en; + input i; + output o; + + assign o = en ? i : 1'bz; + +endmodule + + +module top ( +input en, +input a, +output b +); + +tristate u_tri ( + .en (en ), + .i (a ), + .o (b ) + ); + +endmodule diff --git a/tests/ecp5/tribuf.ys b/tests/ecp5/tribuf.ys new file mode 100644 index 000000000..f454a0c02 --- /dev/null +++ b/tests/ecp5/tribuf.ys @@ -0,0 +1,9 @@ +read_verilog tribuf.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v -map +/simcells.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:$_TBUF_ +select -assert-none t:$_TBUF_ %% t:* %D |