| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Moved all tests in arch sub directory | Miodrag Milanovic | 2019-10-18 | 32 | -668/+0 |
| * | Add async2sync | Miodrag Milanovic | 2019-10-18 | 1 | -4/+4 |
| * | hierarchy - proc reorder | Miodrag Milanovic | 2019-10-18 | 9 | -14/+18 |
| * | Check latches type one by one | Miodrag Milanovic | 2019-10-04 | 2 | -40/+25 |
| * | Removed top module where not needed | Miodrag Milanovic | 2019-10-04 | 4 | -37/+4 |
| * | Test muxes synth one by one | Miodrag Milanovic | 2019-10-04 | 2 | -38/+39 |
| * | Cleaned verilog code from not used defines | Miodrag Milanovic | 2019-10-04 | 1 | -6/+0 |
| * | Check for MULT18X18D, since that is working now | Miodrag Milanovic | 2019-10-04 | 2 | -14/+11 |
| * | Check flops one by one | Miodrag Milanovic | 2019-10-04 | 4 | -71/+50 |
| * | Removed alu and div_mod tests as agreed | Miodrag Milanovic | 2019-10-04 | 4 | -57/+0 |
| * | equiv_opt with -assert | Eddie Hung | 2019-09-30 | 1 | -3/+1 |
| * | Update resource count for alu.ys | Eddie Hung | 2019-09-30 | 1 | -3/+3 |
| * | Move $x to end as per 7f0eec8 | Eddie Hung | 2019-09-30 | 1 | -1/+1 |
| * | Update fsm.ys resource count | Eddie Hung | 2019-09-30 | 1 | -3/+3 |
| * | Add comment to dpram test about related issue. | SergeyDegtyar | 2019-09-18 | 1 | -0/+1 |
| * | adffs test update (equiv_opt -multiclock). div_mod test fix | SergeyDegtyar | 2019-09-17 | 3 | -17/+12 |
| * | Remove stat command form shifter.ys test | SergeyDegtyar | 2019-09-04 | 1 | -1/+1 |
| * | Fix ecp5 tests | SergeyDegtyar | 2019-09-04 | 11 | -2421/+26 |
| * | Uncomment sat command in memory.ys test. | SergeyDegtyar | 2019-09-03 | 1 | -2/+1 |
| * | Add tests for ECP5 architecture | SergeyDegtyar | 2019-09-03 | 39 | -0/+3200 |
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |