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-rw-r--r--passes/memory/memory_collect.cc4
1 files changed, 4 insertions, 0 deletions
diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc
index 6acbce62f..9dcb3f024 100644
--- a/passes/memory/memory_collect.cc
+++ b/passes/memory/memory_collect.cc
@@ -218,6 +218,10 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory)
mem->setPort("\\RD_DATA", sig_rd_data);
mem->setPort("\\RD_EN", sig_rd_en);
+ // Copy attributes from RTLIL memory to $mem
+ for (auto attr : memory->attributes)
+ mem->attributes[attr.first] = attr.second;
+
for (auto c : memcells)
module->remove(c);