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| author | David Shah <dave@ds0.me> | 2019-11-18 13:58:03 +0000 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2019-11-18 13:58:03 +0000 |
| commit | 7ff5d6d30ae9f48376f0c6a98d8a5fa0831faf77 (patch) | |
| tree | 29ee366e0d82b9dae913f896b688ea80b00ec130 /passes/memory/memory_collect.cc | |
| parent | 9ee3c57e460b15acb8e1503e97fc35aa6eed0661 (diff) | |
| download | yosys-7ff5d6d30ae9f48376f0c6a98d8a5fa0831faf77.tar.gz yosys-7ff5d6d30ae9f48376f0c6a98d8a5fa0831faf77.tar.bz2 yosys-7ff5d6d30ae9f48376f0c6a98d8a5fa0831faf77.zip | |
memory_collect: Copy attr from RTLIL::Memory to cell
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'passes/memory/memory_collect.cc')
| -rw-r--r-- | passes/memory/memory_collect.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index 6acbce62f..9dcb3f024 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -218,6 +218,10 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory) mem->setPort("\\RD_DATA", sig_rd_data); mem->setPort("\\RD_EN", sig_rd_en); + // Copy attributes from RTLIL memory to $mem + for (auto attr : memory->attributes) + mem->attributes[attr.first] = attr.second; + for (auto c : memcells) module->remove(c); |