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-rw-r--r--frontends/verilog/verilog_parser.y2
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 15c231f3b..6687a195e 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -435,7 +435,7 @@ module:
mod->str = *$4;
append_attr(mod, $1);
delete $4;
- } module_para_opt module_args_opt ';' module_body TOK_ENDMODULE {
+ } module_para_opt module_args_opt ';' module_body TOK_ENDMODULE opt_label {
if (port_stubs.size() != 0)
frontend_verilog_yyerror("Missing details for module port `%s'.",
port_stubs.begin()->first.c_str());