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| author | whitequark <whitequark@whitequark.org> | 2020-01-01 09:48:39 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-04-03 05:51:40 +0000 |
| commit | ebee746ad21b9f1fe37f50908bdc5d219880e6bb (patch) | |
| tree | f18a6d151d8d09b335a98ad3d723dd158f4692cc /tests | |
| parent | e0def9e4d93bc99a65c3c918b53fee17fbe3a2ba (diff) | |
| download | yosys-ebee746ad21b9f1fe37f50908bdc5d219880e6bb.tar.gz yosys-ebee746ad21b9f1fe37f50908bdc5d219880e6bb.tar.bz2 yosys-ebee746ad21b9f1fe37f50908bdc5d219880e6bb.zip | |
ice40: do not map FFRAM if explicitly requested otherwise.
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/arch/ice40/memories.ys | 36 |
1 files changed, 28 insertions, 8 deletions
diff --git a/tests/arch/ice40/memories.ys b/tests/arch/ice40/memories.ys index 86a60b258..571edec1d 100644 --- a/tests/arch/ice40/memories.ys +++ b/tests/arch/ice40/memories.ys @@ -65,15 +65,25 @@ design -reset; read_verilog ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp setattr -set syn_romstyle "ebr" m:memory synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp -select -assert-count 0 t:SB_RAM40_4K # requested BROM but this is a RAM -select -assert-min 1 t:SB_DFFE +select -assert-count 1 t:$mem # requested BROM but this is a RAM design -reset; read_verilog ../common/blockram.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp setattr -set rom_block 1 m:memory synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp -select -assert-count 0 t:SB_RAM40_4K # requested BROM but this is a RAM -select -assert-min 1 t:SB_DFFE +select -assert-count 1 t:$mem # requested BROM but this is a RAM + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp +setattr -set syn_ramstyle "block_ram" m:memory +synth_ice40 -top sync_ram_sdp -nobram; cd sync_ram_sdp +select -assert-count 1 t:$mem # requested BRAM but BRAM is disabled + +design -reset; read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp +setattr -set ram_block 1 m:memory +synth_ice40 -top sync_ram_sdp -nobram; cd sync_ram_sdp +select -assert-count 1 t:$mem # requested BRAM but BRAM is disabled # ================================ ROM ================================ # ROM bits <= 4K; Data width <= 16; Address width <= 11: -> SB_RAM40_4K @@ -137,12 +147,22 @@ design -reset; read_verilog ../common/blockrom.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom setattr -set syn_ramstyle "block_ram" m:memory synth_ice40 -top sync_rom; cd sync_rom -select -assert-count 0 t:SB_RAM40_4K # requested BRAM but this is a ROM -select -assert-min 1 t:SB_LUT4 +select -assert-count 1 t:$mem # requested BRAM but this is a ROM design -reset; read_verilog ../common/blockrom.v chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom setattr -set ram_block 1 m:memory synth_ice40 -top sync_rom; cd sync_rom -select -assert-count 0 t:SB_RAM40_4K # requested BRAM but this is a ROM -select -assert-min 1 t:SB_LUT4 +select -assert-count 1 t:$mem # requested BRAM but this is a ROM + +design -reset; read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom +setattr -set syn_romstyle "ebr" m:memory +synth_ice40 -top sync_rom -nobram; cd sync_rom +select -assert-count 1 t:$mem # requested BROM but BRAM is disabled + +design -reset; read_verilog ../common/blockrom.v +chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom +setattr -set rom_block 1 m:memory +synth_ice40 -top sync_rom -nobram; cd sync_rom +select -assert-count 1 t:$mem # requested BROM but BRAM is disabled |