From ebee746ad21b9f1fe37f50908bdc5d219880e6bb Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 1 Jan 2020 09:48:39 +0000
Subject: ice40: do not map FFRAM if explicitly requested otherwise.

---
 tests/arch/ice40/memories.ys | 36 ++++++++++++++++++++++++++++--------
 1 file changed, 28 insertions(+), 8 deletions(-)

(limited to 'tests')

diff --git a/tests/arch/ice40/memories.ys b/tests/arch/ice40/memories.ys
index 86a60b258..571edec1d 100644
--- a/tests/arch/ice40/memories.ys
+++ b/tests/arch/ice40/memories.ys
@@ -65,15 +65,25 @@ design -reset; read_verilog ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
 setattr -set syn_romstyle "ebr" m:memory
 synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 0 t:SB_RAM40_4K # requested BROM but this is a RAM
-select -assert-min 1 t:SB_DFFE
+select -assert-count 1 t:$mem # requested BROM but this is a RAM
 
 design -reset; read_verilog ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
 setattr -set rom_block 1 m:memory
 synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
-select -assert-count 0 t:SB_RAM40_4K # requested BROM but this is a RAM
-select -assert-min 1 t:SB_DFFE
+select -assert-count 1 t:$mem # requested BROM but this is a RAM
+
+design -reset; read_verilog ../common/blockram.v
+chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
+setattr -set syn_ramstyle "block_ram" m:memory
+synth_ice40 -top sync_ram_sdp -nobram; cd sync_ram_sdp
+select -assert-count 1 t:$mem # requested BRAM but BRAM is disabled
+
+design -reset; read_verilog ../common/blockram.v
+chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
+setattr -set ram_block 1 m:memory
+synth_ice40 -top sync_ram_sdp -nobram; cd sync_ram_sdp
+select -assert-count 1 t:$mem # requested BRAM but BRAM is disabled
 
 # ================================ ROM ================================
 # ROM bits <= 4K; Data width <= 16; Address width <= 11: -> SB_RAM40_4K
@@ -137,12 +147,22 @@ design -reset; read_verilog ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
 setattr -set syn_ramstyle "block_ram" m:memory
 synth_ice40 -top sync_rom; cd sync_rom
-select -assert-count 0 t:SB_RAM40_4K # requested BRAM but this is a ROM
-select -assert-min 1 t:SB_LUT4
+select -assert-count 1 t:$mem # requested BRAM but this is a ROM
 
 design -reset; read_verilog ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
 setattr -set ram_block 1 m:memory
 synth_ice40 -top sync_rom; cd sync_rom
-select -assert-count 0 t:SB_RAM40_4K # requested BRAM but this is a ROM
-select -assert-min 1 t:SB_LUT4
+select -assert-count 1 t:$mem # requested BRAM but this is a ROM
+
+design -reset; read_verilog ../common/blockrom.v
+chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
+setattr -set syn_romstyle "ebr" m:memory
+synth_ice40 -top sync_rom -nobram; cd sync_rom
+select -assert-count 1 t:$mem # requested BROM but BRAM is disabled
+
+design -reset; read_verilog ../common/blockrom.v
+chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
+setattr -set rom_block 1 m:memory
+synth_ice40 -top sync_rom -nobram; cd sync_rom
+select -assert-count 1 t:$mem # requested BROM but BRAM is disabled
-- 
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