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| author | Claire Wolf <clifford@clifford.at> | 2020-04-22 16:57:34 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-04-22 16:57:34 +0200 |
| commit | c32b4bded582e121056a497131bf617684448cc4 (patch) | |
| tree | 1ff19093149061387ee969ec2b898a7a0f2f4112 /tests | |
| parent | 95c74b319b36f8cb950196c3e1d10c945629c1f5 (diff) | |
| parent | abf81c76396d674833d1dce3f3f75a43f76e2a1f (diff) | |
| download | yosys-c32b4bded582e121056a497131bf617684448cc4.tar.gz yosys-c32b4bded582e121056a497131bf617684448cc4.tar.bz2 yosys-c32b4bded582e121056a497131bf617684448cc4.zip | |
Merge pull request #1976 from YosysHQ/dave/fix-sim-const
sim: Fix handling of constant-connected cell inputs at startup
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/various/sim_const.ys | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/tests/various/sim_const.ys b/tests/various/sim_const.ys new file mode 100644 index 000000000..d778b92cd --- /dev/null +++ b/tests/various/sim_const.ys @@ -0,0 +1,13 @@ +read_verilog <<EOT + +module top(input clk, output reg [1:0] q); + wire [1:0] x = 2'b10; + always @(posedge clk) + q <= x & 2'b11; +endmodule +EOT + +proc +sim -clock clk -n 1 -w top +select -assert-count 1 a:init=2'b10 top/q %i + |