From abf81c76396d674833d1dce3f3f75a43f76e2a1f Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Tue, 21 Apr 2020 08:58:52 +0100
Subject: sim: Fix handling of constant-connected cell inputs at startup

Signed-off-by: David Shah <dave@ds0.me>
---
 tests/various/sim_const.ys | 13 +++++++++++++
 1 file changed, 13 insertions(+)
 create mode 100644 tests/various/sim_const.ys

(limited to 'tests')

diff --git a/tests/various/sim_const.ys b/tests/various/sim_const.ys
new file mode 100644
index 000000000..d778b92cd
--- /dev/null
+++ b/tests/various/sim_const.ys
@@ -0,0 +1,13 @@
+read_verilog <<EOT
+
+module top(input clk, output reg [1:0] q);
+	wire [1:0] x = 2'b10;
+	always @(posedge clk)
+		q <= x & 2'b11;
+endmodule
+EOT
+
+proc
+sim -clock clk -n 1 -w top
+select -assert-count 1 a:init=2'b10 top/q %i
+
-- 
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