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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-25 07:32:27 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-25 08:43:33 -0700 |
| commit | 9c6d216a063452fcf0061b593b8ac278a39ff194 (patch) | |
| tree | 8f681b0babd9d281ac2259213e0503b23e16c31e /tests | |
| parent | 7bad23f19cb6d7cfcc2245827f5687142209fe87 (diff) | |
| download | yosys-9c6d216a063452fcf0061b593b8ac278a39ff194.tar.gz yosys-9c6d216a063452fcf0061b593b8ac278a39ff194.tar.bz2 yosys-9c6d216a063452fcf0061b593b8ac278a39ff194.zip | |
tests: add test for abc9 -dff removing a redundant flop entirely
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/arch/xilinx/abc9_dff.ys | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/tests/arch/xilinx/abc9_dff.ys b/tests/arch/xilinx/abc9_dff.ys index c549e1fdc..e3889be05 100644 --- a/tests/arch/xilinx/abc9_dff.ys +++ b/tests/arch/xilinx/abc9_dff.ys @@ -116,4 +116,19 @@ design -load postopt select -assert-count 1 t:FDRE %co %a w:r %i +design -reset +read_verilog <<EOT +module top(input clk, input a, b, output o); +reg r1, r2; +always @(posedge clk) begin + r1 <= a | b; + r2 <= ~(~a & ~b); +end +assign o = r1 | r2; +endmodule +EOT +proc +equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf + + logger -expect-no-warnings |