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| author | whitequark <whitequark@whitequark.org> | 2020-05-05 04:11:16 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-05-05 04:16:59 +0000 |
| commit | 66d0ed2bcc7195aab5b107b2536e6818fe5b244c (patch) | |
| tree | 2241c2fdc50c94b277774292d4cbc67ba109f712 /tests | |
| parent | d1c8837572fb343baccff4d766a8aa0bca26aab7 (diff) | |
| download | yosys-66d0ed2bcc7195aab5b107b2536e6818fe5b244c.tar.gz yosys-66d0ed2bcc7195aab5b107b2536e6818fe5b244c.tar.bz2 yosys-66d0ed2bcc7195aab5b107b2536e6818fe5b244c.zip | |
ast/simplify: don't bitblast async ROMs declared as `logic`.
Fixes #2020.
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/svtypes/logic_rom.sv | 6 | ||||
| -rw-r--r-- | tests/svtypes/logic_rom.ys | 3 |
2 files changed, 9 insertions, 0 deletions
diff --git a/tests/svtypes/logic_rom.sv b/tests/svtypes/logic_rom.sv new file mode 100644 index 000000000..45fe0a4ca --- /dev/null +++ b/tests/svtypes/logic_rom.sv @@ -0,0 +1,6 @@ +module top(input [3:0] addr, output [7:0] data); + logic [7:0] mem[0:15]; + assign data = mem[addr]; + integer i; + initial for(i = 0; i < 16; i = i + 1) mem[i] = i; +endmodule diff --git a/tests/svtypes/logic_rom.ys b/tests/svtypes/logic_rom.ys new file mode 100644 index 000000000..7b079c136 --- /dev/null +++ b/tests/svtypes/logic_rom.ys @@ -0,0 +1,3 @@ +read_verilog -sv logic_rom.sv +prep -top top +select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=8 %i |