From 66d0ed2bcc7195aab5b107b2536e6818fe5b244c Mon Sep 17 00:00:00 2001 From: whitequark Date: Tue, 5 May 2020 04:11:16 +0000 Subject: ast/simplify: don't bitblast async ROMs declared as `logic`. Fixes #2020. --- tests/svtypes/logic_rom.sv | 6 ++++++ tests/svtypes/logic_rom.ys | 3 +++ 2 files changed, 9 insertions(+) create mode 100644 tests/svtypes/logic_rom.sv create mode 100644 tests/svtypes/logic_rom.ys (limited to 'tests') diff --git a/tests/svtypes/logic_rom.sv b/tests/svtypes/logic_rom.sv new file mode 100644 index 000000000..45fe0a4ca --- /dev/null +++ b/tests/svtypes/logic_rom.sv @@ -0,0 +1,6 @@ +module top(input [3:0] addr, output [7:0] data); + logic [7:0] mem[0:15]; + assign data = mem[addr]; + integer i; + initial for(i = 0; i < 16; i = i + 1) mem[i] = i; +endmodule diff --git a/tests/svtypes/logic_rom.ys b/tests/svtypes/logic_rom.ys new file mode 100644 index 000000000..7b079c136 --- /dev/null +++ b/tests/svtypes/logic_rom.ys @@ -0,0 +1,3 @@ +read_verilog -sv logic_rom.sv +prep -top top +select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=8 %i -- cgit v1.2.3