From 5a00d5578cea91ce84f3d95e6138c85d1a949b89 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 16 Dec 2019 13:31:15 -0800 Subject: Add unconditional match blocks for force RAM --- tests/arch/xilinx/blockram.ys | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'tests') diff --git a/tests/arch/xilinx/blockram.ys b/tests/arch/xilinx/blockram.ys index 362d33229..b6e105854 100644 --- a/tests/arch/xilinx/blockram.ys +++ b/tests/arch/xilinx/blockram.ys @@ -79,3 +79,12 @@ setattr -set logic_block 1 m:memory synth_xilinx -top sync_ram_sdp cd sync_ram_sdp select -assert-count 0 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram.v +hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 8 -chparam DATA_WIDTH 1 +setattr -set ram_style "block" m:memory +dump m:* +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 -- cgit v1.2.3