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| author | Clifford Wolf <clifford@clifford.at> | 2019-03-30 00:09:42 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-03-30 00:09:42 +0100 |
| commit | 22035c20ff071ec5c30990258850ecf97de5d5b3 (patch) | |
| tree | 35cd5485c70c17e93426d54a104018bae90ed924 /tests | |
| parent | 32bd0f22ec93202e67395901cdc64c20df7f0da7 (diff) | |
| parent | 584d2030bf53c703febe8fda9cae73c72416c6cc (diff) | |
| download | yosys-22035c20ff071ec5c30990258850ecf97de5d5b3.tar.gz yosys-22035c20ff071ec5c30990258850ecf97de5d5b3.tar.bz2 yosys-22035c20ff071ec5c30990258850ecf97de5d5b3.zip | |
Merge pull request #907 from YosysHQ/clifford/fix906
Build Verilog parser with -DYYMAXDEPTH=100000
Diffstat (limited to 'tests')
0 files changed, 0 insertions, 0 deletions