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| author | Clifford Wolf <clifford@clifford.at> | 2019-03-29 16:32:44 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-03-29 16:32:44 +0100 |
| commit | 584d2030bf53c703febe8fda9cae73c72416c6cc (patch) | |
| tree | 35cd5485c70c17e93426d54a104018bae90ed924 /tests | |
| parent | 32bd0f22ec93202e67395901cdc64c20df7f0da7 (diff) | |
| download | yosys-584d2030bf53c703febe8fda9cae73c72416c6cc.tar.gz yosys-584d2030bf53c703febe8fda9cae73c72416c6cc.tar.bz2 yosys-584d2030bf53c703febe8fda9cae73c72416c6cc.zip | |
Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'tests')
0 files changed, 0 insertions, 0 deletions