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| author | Jannis Harder <me@jix.one> | 2023-01-29 13:54:02 +0100 |
|---|---|---|
| committer | Jannis Harder <me@jix.one> | 2023-01-29 14:02:25 +0100 |
| commit | b08a8807044980b7906362848f62291ede50e696 (patch) | |
| tree | daafa09056ad4efef3860a883b9f52843a91670c /tests/various/rtlil_z_bits.ys | |
| parent | 541fdffff243bccb410de13ae3ef91797060fcd4 (diff) | |
| download | yosys-b08a8807044980b7906362848f62291ede50e696.tar.gz yosys-b08a8807044980b7906362848f62291ede50e696.tar.bz2 yosys-b08a8807044980b7906362848f62291ede50e696.zip | |
backends/rtlil: Do not shorten a value with z bits to 'x
Diffstat (limited to 'tests/various/rtlil_z_bits.ys')
| -rw-r--r-- | tests/various/rtlil_z_bits.ys | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/tests/various/rtlil_z_bits.ys b/tests/various/rtlil_z_bits.ys new file mode 100644 index 000000000..c38669159 --- /dev/null +++ b/tests/various/rtlil_z_bits.ys @@ -0,0 +1,9 @@ +! mkdir -p temp +read_rtlil <<EOT +module \test + wire output 1 \a + connect \a 1'z +end +EOT +write_rtlil temp/rtlil_z_bits.il +! grep -F -q "connect \\a 1'z" temp/rtlil_z_bits.il |