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author | Clifford Wolf <clifford@clifford.at> | 2017-07-28 15:33:30 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2017-07-28 17:39:43 +0200 |
commit | 4cf890dac121dc977fc4507168b48e47aecf5c46 (patch) | |
tree | 35f53140121d1d2eb6e0412f994b31d8562b2a43 /tests/sva/.gitignore | |
parent | 5a828fff34ae8e0da7d887232daa516db1e37a21 (diff) | |
download | yosys-4cf890dac121dc977fc4507168b48e47aecf5c46.tar.gz yosys-4cf890dac121dc977fc4507168b48e47aecf5c46.tar.bz2 yosys-4cf890dac121dc977fc4507168b48e47aecf5c46.zip |
Add simple VHDL+PSL example
Diffstat (limited to 'tests/sva/.gitignore')
-rw-r--r-- | tests/sva/.gitignore | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/tests/sva/.gitignore b/tests/sva/.gitignore index 254013047..cc254049a 100644 --- a/tests/sva/.gitignore +++ b/tests/sva/.gitignore @@ -3,3 +3,5 @@ /*_pass /*_fail /*.ok +/vhdlpsl[0-9][0-9] +/vhdlpsl[0-9][0-9].sby |