Merge branch 'xaig_dff' of github.com:YosysHQ/yosys into xaig_dff

1 files changed, 7 insertions, 7 deletions

diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v
index 8314af211..99075d319 100644
--- a/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@ -268,23 +268,23 @@ assign o = { 1'b1, 1'bx };
 assign p = { 1'b1, 1'bx, 1'b0 };
 endmodule
 
-module abc9_test029(input clk, d, r, output reg q);
+module abc9_test029(input clk1, clk2, d, output reg q1, q2);
+always @(posedge clk1) q1 <= d;
+always @(negedge clk2) q2 <= q1;
+endmodule
+
+module abc9_test030(input clk, d, r, output reg q);
 always @(posedge clk or posedge r)
     if (r) q <= 1'b0;
     else q <= d;
 endmodule
 
-module abc9_test030(input clk, d, r, output reg q);
+module abc9_test031(input clk, d, r, output reg q);
 always @(negedge clk or posedge r)
     if (r) q <= 1'b1;
     else q <= d;
 endmodule
 
-module abc9_test032(input clk1, clk2, d, output reg q1, q2);
-always @(posedge clk1) q1 <= d;
-always @(negedge clk2) q2 <= q1;
-endmodule
-
 module abc9_test033(input clk, d, output reg q1, q2);
 always @(posedge clk) q1 <= d;
 always @(posedge clk) q2 <= q1;