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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-23 08:22:03 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-11-23 08:22:03 -0800 |
| commit | 23fcdd96b3fda06bb9400b9b729f8a86a3725e84 (patch) | |
| tree | fb3c0623c1c46fcc4d0c5777472c3fcf9fbdd52e /tests/simple_abc9 | |
| parent | a5767474830756319ce0fff53b81573701ec0cd2 (diff) | |
| parent | 6841e3b1c2b2bc3124810f3a8f96ed00a96e954c (diff) | |
| download | yosys-23fcdd96b3fda06bb9400b9b729f8a86a3725e84.tar.gz yosys-23fcdd96b3fda06bb9400b9b729f8a86a3725e84.tar.bz2 yosys-23fcdd96b3fda06bb9400b9b729f8a86a3725e84.zip | |
Merge pull request #1505 from YosysHQ/eddie/xaig_dff_adff
xaig_dff to support async flops $_DFF_[NP][NP][01]_
Diffstat (limited to 'tests/simple_abc9')
| -rw-r--r-- | tests/simple_abc9/abc9.v | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index 1844bac20..65eb01338 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -272,3 +272,15 @@ module abc9_test029(input clk1, clk2, input d, output reg q1, q2); always @(posedge clk1) q1 <= d; always @(negedge clk2) q2 <= q1; endmodule + +module abc9_test030(input clk, d, r, output reg q); +always @(posedge clk or posedge r) + if (r) q <= 1'b0; + else q <= d; +endmodule + +module abc9_test031(input clk, d, r, output reg q); +always @(negedge clk or posedge r) + if (r) q <= 1'b1; + else q <= d; +endmodule |