From 00a6c1d9a57da0e0b0fef07b2d618847ed93a9fd Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 9 Jul 2013 14:31:57 +0200 Subject: Major redesign of expr width/sign detecion (verilog/ast frontend) --- tests/simple/signedexpr.v | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 tests/simple/signedexpr.v (limited to 'tests/simple') diff --git a/tests/simple/signedexpr.v b/tests/simple/signedexpr.v new file mode 100644 index 000000000..3eb5e93df --- /dev/null +++ b/tests/simple/signedexpr.v @@ -0,0 +1,18 @@ +module test01(a, b, xu, xs, yu, ys, zu, zs); + +input signed [1:0] a; +input signed [2:0] b; +output [3:0] xu, xs; +output [3:0] yu, ys; +output zu, zs; + +assign xu = (a + b) + 3'd0; +assign xs = (a + b) + 3'sd0; + +assign yu = {a + b} + 3'd0; +assign ys = {a + b} + 3'sd0; + +assign zu = a + b != 3'd0; +assign zs = a + b != 3'sd0; + +endmodule -- cgit v1.2.3