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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-24 15:05:44 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-24 15:05:44 -0700 |
| commit | dc87372a97d515563ccccd517ef8f35662870fe6 (patch) | |
| tree | 9373bef80912453fd62497555dd97ab52f72d18e /tests/sat | |
| parent | 10c41a5cf51427d96f465113decb752e501e926e (diff) | |
| download | yosys-dc87372a97d515563ccccd517ef8f35662870fe6.tar.gz yosys-dc87372a97d515563ccccd517ef8f35662870fe6.tar.bz2 yosys-dc87372a97d515563ccccd517ef8f35662870fe6.zip | |
Wire with init on FF part, 1'bx on non-FF part
Diffstat (limited to 'tests/sat')
| -rw-r--r-- | tests/sat/initval.v | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/tests/sat/initval.v b/tests/sat/initval.v index fcec9dd8c..81f71b5ba 100644 --- a/tests/sat/initval.v +++ b/tests/sat/initval.v @@ -1,4 +1,4 @@ -module test(input clk, input [3:0] bar, output [3:0] foo); +module test(input clk, input [3:0] bar, output [3:0] foo, asdf); reg [3:0] foo = 0; reg [3:0] last_bar = 0; reg [3:0] asdf = 4'b1xxx; @@ -12,6 +12,8 @@ module test(input clk, input [3:0] bar, output [3:0] foo); always @(posedge clk) last_bar <= bar; + always @(posedge clk) + asdf[3] <= bar[3]; always @* asdf[2:0] = 3'b111; |