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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 09:11:04 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-23 09:11:04 -0700 |
| commit | 10c41a5cf51427d96f465113decb752e501e926e (patch) | |
| tree | ef9466069ce2face060833b7de50c6f561f6db60 /tests/sat | |
| parent | 51ffb093b5beeb5e2c687d2bf34b13d246f3fc7d (diff) | |
| download | yosys-10c41a5cf51427d96f465113decb752e501e926e.tar.gz yosys-10c41a5cf51427d96f465113decb752e501e926e.tar.bz2 yosys-10c41a5cf51427d96f465113decb752e501e926e.zip | |
Blocking assignment
Diffstat (limited to 'tests/sat')
| -rw-r--r-- | tests/sat/initval.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/sat/initval.v b/tests/sat/initval.v index d46ccae48..fcec9dd8c 100644 --- a/tests/sat/initval.v +++ b/tests/sat/initval.v @@ -13,7 +13,7 @@ module test(input clk, input [3:0] bar, output [3:0] foo); last_bar <= bar; always @* - asdf[2:0] <= 3'b111; + asdf[2:0] = 3'b111; assert property (foo == {last_bar[3:2], bar[1:0]}); endmodule |