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| author | whitequark <whitequark@whitequark.org> | 2018-12-05 04:50:38 +0000 |
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| committer | whitequark <whitequark@whitequark.org> | 2018-12-05 17:13:27 +0000 |
| commit | 9ef078848a5b121336b83043c565ce47433eb2d8 (patch) | |
| tree | fdfa9d1c1fbe809815e8a26310d8197f3695cee6 /tests/lut/map_xor.v | |
| parent | 12596b5003bcc6180cda04ce2aaaa2a8145f8a9b (diff) | |
| download | yosys-9ef078848a5b121336b83043c565ce47433eb2d8.tar.gz yosys-9ef078848a5b121336b83043c565ce47433eb2d8.tar.bz2 yosys-9ef078848a5b121336b83043c565ce47433eb2d8.zip | |
gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.
Diffstat (limited to 'tests/lut/map_xor.v')
| -rw-r--r-- | tests/lut/map_xor.v | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/tests/lut/map_xor.v b/tests/lut/map_xor.v new file mode 100644 index 000000000..708a05789 --- /dev/null +++ b/tests/lut/map_xor.v @@ -0,0 +1,5 @@ +module top(...); + input a, b; + output y; + assign y = a^b; +endmodule |