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author | whitequark <whitequark@whitequark.org> | 2018-12-05 04:50:38 +0000 |
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committer | whitequark <whitequark@whitequark.org> | 2018-12-05 17:13:27 +0000 |
commit | 9ef078848a5b121336b83043c565ce47433eb2d8 (patch) | |
tree | fdfa9d1c1fbe809815e8a26310d8197f3695cee6 /tests/lut | |
parent | 12596b5003bcc6180cda04ce2aaaa2a8145f8a9b (diff) | |
download | yosys-9ef078848a5b121336b83043c565ce47433eb2d8.tar.gz yosys-9ef078848a5b121336b83043c565ce47433eb2d8.tar.bz2 yosys-9ef078848a5b121336b83043c565ce47433eb2d8.zip |
gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.
Diffstat (limited to 'tests/lut')
-rw-r--r-- | tests/lut/.gitignore | 1 | ||||
-rw-r--r-- | tests/lut/check_map.ys | 13 | ||||
-rw-r--r-- | tests/lut/map_and.v | 5 | ||||
-rw-r--r-- | tests/lut/map_mux.v | 5 | ||||
-rw-r--r-- | tests/lut/map_not.v | 5 | ||||
-rw-r--r-- | tests/lut/map_or.v | 5 | ||||
-rw-r--r-- | tests/lut/map_xor.v | 5 | ||||
-rw-r--r-- | tests/lut/run-test.sh | 6 |
8 files changed, 45 insertions, 0 deletions
diff --git a/tests/lut/.gitignore b/tests/lut/.gitignore new file mode 100644 index 000000000..397b4a762 --- /dev/null +++ b/tests/lut/.gitignore @@ -0,0 +1 @@ +*.log diff --git a/tests/lut/check_map.ys b/tests/lut/check_map.ys new file mode 100644 index 000000000..6d659891f --- /dev/null +++ b/tests/lut/check_map.ys @@ -0,0 +1,13 @@ +design -save preopt + +simplemap +techmap -map +/gate2lut.v -D LUT_WIDTH=4 +select -assert-count 1 t:$lut +design -stash postopt + +design -copy-from preopt -as preopt top +design -copy-from postopt -as postopt top +equiv_make preopt postopt equiv +prep -flatten -top equiv +equiv_induct +equiv_status -assert diff --git a/tests/lut/map_and.v b/tests/lut/map_and.v new file mode 100644 index 000000000..68ae33fd6 --- /dev/null +++ b/tests/lut/map_and.v @@ -0,0 +1,5 @@ +module top(...); + input a, b; + output y; + assign y = a&b; +endmodule diff --git a/tests/lut/map_mux.v b/tests/lut/map_mux.v new file mode 100644 index 000000000..ccecf3023 --- /dev/null +++ b/tests/lut/map_mux.v @@ -0,0 +1,5 @@ +module top(...); + input a, b, s; + output y; + assign y = s?a:b; +endmodule diff --git a/tests/lut/map_not.v b/tests/lut/map_not.v new file mode 100644 index 000000000..385997414 --- /dev/null +++ b/tests/lut/map_not.v @@ -0,0 +1,5 @@ +module top(...); + input a; + output y; + assign y = ~a; +endmodule diff --git a/tests/lut/map_or.v b/tests/lut/map_or.v new file mode 100644 index 000000000..8b8c55188 --- /dev/null +++ b/tests/lut/map_or.v @@ -0,0 +1,5 @@ +module top(...); + input a, b; + output y; + assign y = a|b; +endmodule diff --git a/tests/lut/map_xor.v b/tests/lut/map_xor.v new file mode 100644 index 000000000..708a05789 --- /dev/null +++ b/tests/lut/map_xor.v @@ -0,0 +1,5 @@ +module top(...); + input a, b; + output y; + assign y = a^b; +endmodule diff --git a/tests/lut/run-test.sh b/tests/lut/run-test.sh new file mode 100644 index 000000000..207417fa6 --- /dev/null +++ b/tests/lut/run-test.sh @@ -0,0 +1,6 @@ +#!/bin/bash +set -e +for x in *.v; do + echo "Running $x.." + ../../yosys -q -s check_map.ys -l ${x%.v}.log $x +done |